/*!
* @file     Icu_TmrTypes.h
*
* @version  1.0.0
*
* @brief    Header file of Icu type struct with TMR driver
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef ICU_TMR_TYPE_H
#define ICU_TMR_TYPE_H

#ifdef __cplusplus
extern "C"{
#endif

#include "Icu_Cfg.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup ICU_Driver
  * @brief ICU driver modules
  @{
*/

/** @defgroup ICU_Macros
  @{
*/
/**************************************************************************
                  VENDOR ID & AUTOSAR VERSION INFO
**************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define ICU_TMR_TYPE_H_VENDOR_ID                       0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */
#define ICU_TMR_TYPE_H_AR_RELEASE_MAJOR_VERSION        0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define ICU_TMR_TYPE_H_AR_RELEASE_MINOR_VERSION        0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define ICU_TMR_TYPE_H_AR_RELEASE_REVISION_VERSION     0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define ICU_TMR_TYPE_H_SW_MAJOR_VERSION                0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define ICU_TMR_TYPE_H_SW_MINOR_VERSION                0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define ICU_TMR_TYPE_H_SW_PATCH_VERSION                0x00U

/**@} end of group ICU_Macros */

/**************************************************************************
                    MACRO DEFINITION
**************************************************************************/
/** @defgroup ICU_Macros
  @{
*/

/** the maximum value that CHNV register can increase arrive */
#define ICU_TMR_CC_REG_MAX_VAL          ((uint32)0xFFFFUL)

/**@} end of group ICU_Macros */

/**************************************************************************
                    ENUMERATION DEFINITION
**************************************************************************/
/** @defgroup ICU_Enumerations
  @{
*/

/**
 * @brief   Defines TMR module id.
 */
typedef enum
{
    ICU_TMR0 = (uint8)0x00, //!< TMR module 0(Current not supported)
    ICU_TMR1 = (uint8)0x01, //!< TMR module 1
    ICU_TMR2 = (uint8)0x02, //!< TMR module 2
    ICU_TMR3 = (uint8)0x03, //!< TMR module 3
    ICU_TMR4 = (uint8)0x04  //!< TMR module 4

} Icu_TmrModuleType;

/**
 * @brief   Clock_Division_CKD
 */
typedef enum
{
    ICU_TMR_CKD_DIV1 = 0, //!< TDTS = Tck_tim
    ICU_TMR_CKD_DIV2 = 1, //!< TDTS = 2 * Tck_tim
    ICU_TMR_CKD_DIV4 = 2  //!< TDTS = 4 * Tck_tim
} Icu_TmrFilClkDivType;

/**
 * @brief   Tmr counter_Mode
 */
typedef enum
{
    ICU_TMR_CNTER_MODE_UP = 0,             //!< Timer Up Counting Mode
    ICU_TMR_CNTER_MODE_DOWN = 1,           //!< Timer Down Counting Mode
    ICU_TMR_CNTER_MODE_CENALIGNED1 = 2,    //!< Timer Center Aligned Mode1
    ICU_TMR_CNTER_MODE_CENALIGNED2 = 4,    //!< Timer Center Aligned Mode2
    ICU_TMR_CNTER_MODE_CENALIGNED3 = 6     //!< Timer Center Aligned Mode3
} Icu_TmrCntModeType;

/**
 * @brief TMR Input_Capture_Selection
 */
typedef enum
{
    ICU_TMR_IC_SELECTION_DIRECT_TI = 0x01,   //!< Input capture mapping in TI1
    ICU_TMR_IC_SELECTION_INDIRECT_TI = 0x02, //!< Input capture mapping in TI2
    ICU_TMR_IC_SELECTION_TRC = 0x03          //!< Input capture mapping in TRC
} Icu_TmrIcSelType;

/**
 * @brief TMR_Input_Capture_Prescaler
 */
typedef enum
{
    ICU_TMR_ICPSC_DIV1 = 0x00, //!< No prescaler
    ICU_TMR_ICPSC_DIV2 = 0x01, //!< Capture is done once every 2 events
    ICU_TMR_ICPSC_DIV4 = 0x02, //!< capture is done once every 4 events
    ICU_TMR_ICPSC_DIV8 = 0x03  //!< capture is done once every 8 events
} Icu_TmrIcPscType;

/**
 * @brief    TMR DMA Base Address
 */
typedef enum
{
    TMR_DMABASE_CTRL1 = 0x0000,   //!< TMR CTRL1 DMA base address setup
    TMR_DMABASE_CTRL2 = 0x0001,   //!< TMR CTRL2 DMA base address setup
    TMR_DMABASE_SMCTRL = 0x0002,  //!< TMR SMCTRL DMA base address setup
    TMR_DMABASE_DIEN = 0x0003,    //!< TMR DIEN DMA base address setup
    TMR_DMABASE_STS = 0x0004,     //!< TMR STS DMA base address setup
    TMR_DMABASE_CEG = 0x0005,     //!< TMR CEG DMA base address setup
    TMR_DMABASE_CCM1 = 0x0006,    //!< TMR CCM1 DMA base address setup
    TMR_DMABASE_CCM2 = 0x0007,    //!< TMR CCM2 DMA base address setup 
    TMR_DMABASE_CHCTRL = 0x0008,  //!< TMR CHCTRL DMA base address setup
    TMR_DMABASE_CNT = 0x0009,     //!< TMR CNT DMA base address setup 
    TMR_DMABASE_DIV = 0x000A,     //!< TMR DIV DMA base address setup
    TMR_DMABASE_AUTORLD = 0x000B, //!< TMR AUTORLD DMA base address setup
    TMR_DMABASE_REPCNT = 0x000C,  //!< TMR REPCNT DMA base address setup
    TMR_DMABASE_CH1CC = 0x000D,   //!< TMR CH1CC DMA base address setup
    TMR_DMABASE_CH2CC = 0x000E,   //!< TMR CH2CC DMA base address setup
    TMR_DMABASE_CH3CC = 0x000F,   //!< TMR CH3CC DMA base address setup
    TMR_DMABASE_CH4CC = 0x0010,   //!< TMR CH4CC DMA base address setup
    TMR_DMABASE_BDT = 0x0011,     //!< TMR BDT DMA base address setup
    TMR_DMABASE_DMAB = 0x0012     //!< TMR DMAB DMA base address setup
} Icu_TmrDmaBaseAddrType;

/**
 * @brief    TMR DMA Burst Lenght
 */
typedef enum
{
    TMR_DMA_BURSTLENGHT_1TRANSFER = 0x0000,   //!< Select TMR DMA burst Length 1
    TMR_DMA_BURSTLENGHT_2TRANSFERS = 0x0100,  //!< Select TMR DMA burst Length 2
    TMR_DMA_BURSTLENGHT_3TRANSFERS = 0x0200,  //!< Select TMR DMA burst Length 3
    TMR_DMA_BURSTLENGHT_4TRANSFERS = 0x0300,  //!< Select TMR DMA burst Length 4
    TMR_DMA_BURSTLENGHT_5TRANSFERS = 0x0400,  //!< Select TMR DMA burst Length 5
    TMR_DMA_BURSTLENGHT_6TRANSFERS = 0x0500,  //!< Select TMR DMA burst Length 6
    TMR_DMA_BURSTLENGHT_7TRANSFERS = 0x0600,  //!< Select TMR DMA burst Length 7
    TMR_DMA_BURSTLENGHT_8TRANSFERS = 0x0700,  //!< Select TMR DMA burst Length 8
    TMR_DMA_BURSTLENGHT_9TRANSFERS = 0x0800,  //!< Select TMR DMA burst Length 9
    TMR_DMA_BURSTLENGHT_10TRANSFERS = 0x0900, //!< Select TMR DMA burst Length 10
    TMR_DMA_BURSTLENGHT_11TRANSFERS = 0x0A00, //!< Select TMR DMA burst Length 11
    TMR_DMA_BURSTLENGHT_12TRANSFERS = 0x0B00, //!< Select TMR DMA burst Length 12
    TMR_DMA_BURSTLENGHT_13TRANSFERS = 0x0C00, //!< Select TMR DMA burst Length 13
    TMR_DMA_BURSTLENGHT_14TRANSFERS = 0x0D00, //!< Select TMR DMA burst Length 14
    TMR_DMA_BURSTLENGHT_15TRANSFERS = 0x0E00, //!< Select TMR DMA burst Length 15
    TMR_DMA_BURSTLENGHT_16TRANSFERS = 0x0F00, //!< Select TMR DMA burst Length 16
    TMR_DMA_BURSTLENGHT_17TRANSFERS = 0x1000, //!< Select TMR DMA burst Length 17
    TMR_DMA_BURSTLENGHT_18TRANSFERS = 0x1100  //!< Select TMR DMA burst Length 18
} Icu_TmrDmaBurstLenType;

/**
 * @brief TMR channel id
 */
typedef enum
{
    ICU_TMR_HW_CH1 = 0x01, //!< Channel 1
    ICU_TMR_HW_CH2 = 0x02, //!< Channel 2
    ICU_TMR_HW_CH3 = 0x03, //!< Channel 3
    ICU_TMR_HW_CH4 = 0x04  //!< Channel 4
} Icu_TmrHwChType;

/**
 * @brief TMR channel Input Capture status
 */
typedef enum
{
    TMR_IC_IDLE_STS = 0x00,   //!< TMR channel idle status
    TMR_IC_FIRST_STS = 0x01,  //!< TMR channel first input capture
    TMR_IC_SECOND_STS = 0x02, //!< TMR channel second input capture
    TMR_IC_THIRD_STS = 0x03,  //!< TMR channel third input capture
    TMR_IC_END_STS = 0x04     //!< TMR channel end input capture
} Icu_TmrIcstsType;

/**
 * @brief TMR channel Input Capture Filter configuration
 */
typedef enum
{
    TMR_IC_FILTER_DIS = 0x00, //!< TMR channel Filter disable
    TMR_IC_FILTER_VAL1 = 0x01,//!< TMR channel Filter register:ICxF = 1
    TMR_IC_FILTER_VAL2 = 0x02, //!< TMR channel Filter register:ICxF = 2
    TMR_IC_FILTER_VAL3 = 0x03, //!< TMR channel Filter register:ICxF = 3
    TMR_IC_FILTER_VAL4 = 0x04, //!< TMR channel Filter register:ICxF = 4
    TMR_IC_FILTER_VAL5 = 0x05, //!< TMR channel Filter register:ICxF = 5
    TMR_IC_FILTER_VAL6 = 0x06, //!< TMR channel Filter register:ICxF = 6
    TMR_IC_FILTER_VAL7 = 0x07, //!< TMR channel Filter register:ICxF = 7
    TMR_IC_FILTER_VAL8 = 0x08, //!< TMR channel Filter register:ICxF = 8
    TMR_IC_FILTER_VAL9 = 0x09, //!< TMR channel Filter register:ICxF = 9
    TMR_IC_FILTER_VAL10 = 0x0A,//!< TMR channel Filter register:ICxF = 10
    TMR_IC_FILTER_VAL11 = 0x0B,//!< TMR channel Filter register:ICxF = 11
    TMR_IC_FILTER_VAL12 = 0x0C,//!< TMR channel Filter register:ICxF = 12
    TMR_IC_FILTER_VAL13 = 0x0D,//!< TMR channel Filter register:ICxF = 13
    TMR_IC_FILTER_VAL14 = 0x0E,//!< TMR channel Filter register:ICxF = 14
    TMR_IC_FILTER_VAL15 = 0x0F //!< TMR channel Filter register:ICxF = 15
} Icu_TmrIcFilterType;

/**
 * @brief TMR channel Input Capture Interrupt Type
 */
typedef enum
{
    ICU_TMR_UI_INT = 0x00,
    ICU_TMR_CC_INT = 0x01
} Icu_TmrIcInterruptType;

/**@} end of group ICU_Enumerations */

/**************************************************************************
                    OTHER DEFINITION
**************************************************************************/
/** @defgroup ICU_Structure
  @{
*/

typedef uint8    Icu_TmrChType;
typedef uint16   Icu_TmrPscType;

#if (STD_ON == ICU_TMR_CUSTOM_FEATURE_ENABLE)
typedef void (*Icu_TmrChNotifyFunctionType)(CONST(Icu_TmrModuleType, AUTOMATIC) tmrModule,
                                            CONST(Icu_TmrHwChType, AUTOMATIC) tmrCh);

typedef void (*Icu_TmrOvfNotifyFunctionType)(CONST(Icu_TmrModuleType, AUTOMATIC) tmrModule);
#endif

typedef struct
{
    Icu_TmrIcstsType icuTmrIcSts;          //!< TMR channel input capture status
    uint16 icuTmrIcValFirst;            //!< TMR channel first input capture value
    uint16 icuTmrIcValSecond;           //!< TMR channel second input capture value
    uint32 icuTmrIcOfCnt;               //!< TMR channel input capture overflow value
}Icu_TmrChICCtrlType;

typedef struct
{
    CONST(Icu_TmrModuleType, ICU_CONST) icuTmrModule;           //!< TMR module id
    CONST(Icu_TmrFilClkDivType, ICU_CONST) icuTmrFilClkDiv;     //!< Clock division(for dead region and digital filter)
    CONST(Icu_TmrPscType, ICU_CONST) icuTmrClkPrescale;         //!< Global clock division
    CONST(Icu_TmrCntModeType, ICU_CONST) icuTmrCnterMode;       //!< TMR counter mode selection
    CONST(uint32, ICU_CONST) icuTmrAutoReloadVal;               //!< This must between 0x0000 and 0xFFFF
#if (STD_ON == ICU_DUAL_CLOCK_MODE_API_ENABLE)
    CONST(Icu_TmrPscType, ICU_CONST) icuTmrAltClkPrescale;      //!< Tmr alternative clock division
#endif
#if (STD_ON == ICU_TMR_CUSTOM_FEATURE_ENABLE)
    CONST(Icu_TmrOvfNotifyFunctionType, ICU_CONST) icuTmrOvfNotification; //!< TMR overflow notification function pointer
#endif
}Icu_TmrGlobalCfgType;

typedef struct
{
    //!< ICU TMR channel id(x: 1,2,3,4):
    //!< ICU_TMRx_CH1,
    //!< ICU_TMRx_CH2,
    //!< ICU_TMRx_CH3,
    //!< ICU_TMRx_CH4,
    CONST(uint8, ICU_CONST) icuChannelId;                       //!< ICU TMR channel id
    CONST(Icu_TmrIcPscType, ICU_CONST) icuTmrChPsc;             //!< Specifies the psc
    CONST(Icu_TmrIcSelType, ICU_CONST) icuTmrChInSel;           //!< Specifies the input
    //!< ICU TMR channel default active edge:Must be the same as icuCHActiveEdgeAndWakeup in the 
    //!< Icu_ChCfgType structure in icu.h file:
    //!< ICU_RISING_EDGE,
    //!< ICU_FALLING_EDGE,
    //!< ICU_BOTH_EDGES
    CONST(uint8, ICU_CONST) icuDefaultActiveEdge;
    //!< ICU TMR channel filter:
    //!< ICxF in register TMRm_CCMn (m: 1,2,3,4; n: 1,2; x: 1,2,3,4)
    CONST(Icu_TmrIcFilterType, ICU_CONST) icuTmrChFilter;
    //!< ICU TMR channel mode: Must be the same as icuChModeSelect in the Icu_ChCfgType in icu.h file:
    //!< ICU_MODE_SIGNAL_EDGE_DETECT,
    //!< ICU_MODE_SIGNAL_MEASUREMENT,
    //!< ICU_MODE_TIMESTAMP,
    //!< ICU_MODE_EDGE_COUNTER
    CONST(uint8, ICU_CONST) icuTmrChMode;
#if (STD_ON == ICU_TIMESTAMP_USES_DMA_ENABLE)
    CONST(uint8, ICU_CONST) icuTmrChDmaEnable;   //!< ICU TMR channel DMA enable
#endif

#if (STD_ON == ICU_TMR_CUSTOM_FEATURE_ENABLE)
    CONST(Icu_TmrChNotifyFunctionType, ICU_CONST) icuTmrChNotification; //!< TMR channel notification function pointer
#endif

}Icu_TmrChCfgType;

typedef struct
{
    CONST(Icu_TmrChType, ICU_CONST) totalNumberChannel;  //!< ICU TMR total number channel
    CONST(uint8, ICU_CONST) totalNumberTmr;    //!< ICU TMR total number
#if (STD_ON == ICU_TMR_CUSTOM_FEATURE_ENABLE)
    P2CONST(uint8, ADC_VAR, ICU_APPL_CONST) tmrHwModuleIdToCfgIndexPtr; //!< ICU TMR hardware module id to configured index
#endif
    CONST(Icu_TmrGlobalCfgType, ICU_CONST) (*icuTmrGlobalCfgPtr)[];  //!< ICU TMR global clock
    CONST(Icu_TmrChCfgType, ICU_CONST) (*icuChannelCfgPtr)[];  //!< ICU TMR channel configuration

}Icu_TmrIPCfgType;

/**@} end of group ICU_Structure */

#ifdef __cplusplus
}
#endif

#endif

/**@} end of group ICU_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
