/*!
* @file     Spi_Types.h
*
* @version  1.0.0
*
* @brief    Header file of AUTOSAR Spi driver.This file contains the definitions of SPI peripheral driver used.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_15-Nov-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef SPI_TYPES_H
#define SPI_TYPES_H

#ifdef __cplusplus
extern "C"{
#endif
/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup SPI_Driver
  * @brief SPI driver modules
  @{
*/

/** @defgroup SPI_Macros
  @{
*/
/*******************************************************************************
                  VENDOR ID & AUTOSAR VERSION INFO
*******************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define SPI_TYPES_H_VENDOR_ID                        0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */
#define SPI_TYPES_H_AR_RELEASE_MAJOR_VERSION         0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define SPI_TYPES_H_AR_RELEASE_MINOR_VERSION         0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define SPI_TYPES_H_AR_RELEASE_REVISION_VERSION      0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define SPI_TYPES_H_SW_MAJOR_VERSION                 0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define SPI_TYPES_H_SW_MINOR_VERSION                 0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define SPI_TYPES_H_SW_PATCH_VERSION                 0x00U

/**@} end of group SPI_Macros */
/*******************************************************************************
                    ENUMERATION DEFINITION
*******************************************************************************/
/** @defgroup SPI_Enumerations
  @{
*/
/**
 * @brief   SPI data direction mode
 */
typedef enum
{
    SPI_DIRECTION_2LINES_FULLDUPLEX = ((uint16)0x0000), //!< Full duplex mode,in 2-line unidirectional data mode */
    SPI_DIRECTION_2LINES_RXONLY     = ((uint16)0x0400), //!< Receiver only, in 2-line unidirectional data mode */
    SPI_DIRECTION_1LINE_RX          = ((uint16)0x8000), //!< Receiver mode, in 1 line bidirectional data mode */
    SPI_DIRECTION_1LINE_TX          = ((uint16)0xC000)  //!< Transmit mode, in 1 line bidirectional data mode */
} Spi_DirectionType;

/**
 * @brief   SPI mode
 */
typedef enum
{
    SPI_MODE_SLAVE  = ((uint8)0), //!< Slave mode */
    SPI_MODE_MASTER = ((uint8)1)  //!< Master mode */
} Spi_ModeType;

/**
 * @brief   SPI data length
 */
typedef enum
{
    SPI_DATA_LENGTH_4B    = ((uint8)0x03), //!< Set data length to 4 bits */
    SPI_DATA_LENGTH_5B    = ((uint8)0x04), //!< Set data length to 5 bits */
    SPI_DATA_LENGTH_6B    = ((uint8)0x05), //!< Set data length to 6 bits */
    SPI_DATA_LENGTH_7B    = ((uint8)0x06), //!< Set data length to 7 bits */
    SPI_DATA_LENGTH_8B    = ((uint8)0x07), //!< Set data length to 8 bits */
    SPI_DATA_LENGTH_9B    = ((uint8)0x08), //!< Set data length to 9 bits */
    SPI_DATA_LENGTH_10B   = ((uint8)0x09), //!< Set data length to 10 bits */
    SPI_DATA_LENGTH_11B   = ((uint8)0x0A), //!< Set data length to 11 bits */
    SPI_DATA_LENGTH_12B   = ((uint8)0x0B), //!< Set data length to 12 bits */
    SPI_DATA_LENGTH_13B   = ((uint8)0x0C), //!< Set data length to 13 bits */
    SPI_DATA_LENGTH_14B   = ((uint8)0x0D), //!< Set data length to 14 bits */
    SPI_DATA_LENGTH_15B   = ((uint8)0x0E), //!< Set data length to 15 bits */
    SPI_DATA_LENGTH_16B   = ((uint8)0x0F)  //!< Set data length to 16 bits */
} Spi_DataLenType;

/**
 * @brief   SPI CRC length
 */
typedef enum
{
    SPI_CRC_LENGTH_8B       = ((uint8)0), //!< 8-bit CRC length */
    SPI_CRC_LENGTH_16B      = ((uint8)1)  //!< 16-bit CRC length */
} Spi_CrcLenType;

/**
 * @brief   SPI Clock Polarity
 */
typedef enum
{
    SPI_CLKPOL_LOW          = ((uint8)0), //!< Clock Polarity low */
    SPI_CLKPOL_HIGH         = ((uint8)1)  //!< Clock Polarity high */
} Spi_ClkPolType;

/**
 * @brief   SPI Clock Phase
 */
typedef enum
{
    SPI_CLKPHA_1EDGE        = ((uint8)0), //!< 1 edge clock phase */
    SPI_CLKPHA_2EDGE        = ((uint8)1)  //!< 2 edge clock phase */
} Spi_ClkPhaType;

/**
 * @brief   Software slave control
 */
typedef enum
{
    SPI_SSC_DISABLE         = ((uint8)0), //!< Disable software select slave */
    SPI_SSC_ENABLE          = ((uint8)1) //!< Enable software select slave */
} Spi_SscType;

/**
 * @brief   SPI BaudRate divider
 */
typedef enum
{
    SPI_BAUDRATE_DIV_2      = ((uint8)0), //!< Baud rate divider is 2 */
    SPI_BAUDRATE_DIV_4      = ((uint8)1), //!< Baud rate divider is 4 */
    SPI_BAUDRATE_DIV_8      = ((uint8)2), //!< Baud rate divider is 8 */
    SPI_BAUDRATE_DIV_16     = ((uint8)3), //!< Baud rate divider is 16 */
    SPI_BAUDRATE_DIV_32     = ((uint8)4), //!< Baud rate divider is 32 */
    SPI_BAUDRATE_DIV_64     = ((uint8)5), //!< Baud rate divider is 64 */
    SPI_BAUDRATE_DIV_128    = ((uint8)6), //!< Baud rate divider is 128 */
    SPI_BAUDRATE_DIV_256    = ((uint8)7)  //!< Baud rate divider is 256 */
} Spi_BaudrateDivType;

/**
 * @brief   MSB or LSB is transmitted/received first
 */
typedef enum
{
    SPI_FIRST_BIT_MSB       = ((uint8)0), //!< First bit is MSB */
    SPI_FIRST_BIT_LSB       = ((uint8)1) //!< First bit is LSB */
} Spi_FirstBitType;

/**
 * @brief   SPI FIFO reception threshold
 */
typedef enum
{
    SPI_RXFIFO_HALF         = ((uint8)0), //!< FIFO level is greater than or equal to 1/2 (16-bit) */
    SPI_RXFIFO_QUARTER      = ((uint8)1) //!< FIFO level is greater than or equal to 1/4 (8-bit) */
} Spi_RxFifoType;

/**
 * @brief   SPI last DMA transfers and reception
 */
typedef enum
{
    SPI_LAST_DMA_TXRXEVEN    = ((uint16)0x0000), //!< transmission Even reception Even */
    SPI_LAST_DMA_TXEVENRXODD = ((uint16)0x2000), //!< transmission Even reception Odd */
    SPI_LAST_DMA_TXODDRXEVEN = ((uint16)0x4000), //!< transmission Odd reception Even */
    SPI_LAST_DMA_TXRXODD     = ((uint16)0x6000) //!< transmission Odd reception Odd */
} Spi_LastDmaType;

/**
 * @brief   SPI transmission fifo level
 */
typedef enum
{
    SPI_TXFIFO_LEVEL_EMPTY   = ((uint8)0x00), //!< Transmission FIFO filled level is empty */
    SPI_TXFIFO_LEVEL_QUARTER = ((uint8)0x01), //!< Transmission FIFO filled level is more than quarter */
    SPI_TXFIFO_LEVEL_HALF    = ((uint8)0x02), //!< Transmission FIFO filled level is more than half */
    SPI_TXFIFO_LEVEL_FULL    = ((uint8)0x03) //!< Transmission FIFO filled level is full */
} Spi_TxFifoLevType;

/**
 * @brief   SPI reception fifo level
 */
typedef enum
{
    SPI_RXFIFO_LEVEL_EMPTY    = ((uint8)0x00), //!< Reception FIFO filled level is empty */
    SPI_RXFIFO_LEVEL_QUARTER  = ((uint8)0x01), //!< Reception FIFO filled level is more than quarter */
    SPI_RXFIFO_LEVEL_HALF     = ((uint8)0x02), //!< Reception FIFO filled level is more than half */
    SPI_RXFIFO_LEVEL_FULL     = ((uint8)0x03) //!< Reception FIFO filled level is full */
} Spi_RxFifoLevType;

/**
 * @brief   SPI flags definition
 */
typedef enum
{
    SPI_FLAG_RXBNE      = ((uint16)0x0001), //!< Receive buffer not empty flag */
    SPI_FLAG_TXBE       = ((uint16)0x0002), //!< Transmit buffer empty flag */
    I2S_FLAG_CHDIR      = ((uint16)0x0004), //!< Channel direction flag */
    I2S_FLAG_UDR        = ((uint16)0x0008), //!< Underrun flag */
    SPI_FLAG_CRCE       = ((uint16)0x0010), //!< CRC error flag */
    SPI_FLAG_MME        = ((uint16)0x0020), //!< Master mode error flag */
    SPI_FLAG_OVR        = ((uint16)0x0040), //!< Receive Overrun flag */
    SPI_FLAG_BUSY       = ((uint16)0x0080), //!< Busy flag */
    SPI_FLAG_FFE        = ((uint16)0x0100)  //!< Frame format error flag */
} Spi_FlagType;

/**
 * @brief   SPI interrupt source
 */
typedef enum
{
    SPI_INT_ERRIE       = ((uint8)0x20), //!< Error interrupt */
    SPI_INT_RXBNEIE     = ((uint8)0x40), //!< Receive buffer not empty interrupt */
    SPI_INT_TXBEIE      = ((uint8)0x80)  //!< Transmit buffer empty interrupt */
} Spi_IntType;

/**
 * @brief   SPI interrupt flag
 */
typedef enum
{
    SPI_INT_FLAG_RXBNE      = ((uint32)0x400001), //!< Receive buffer not empty interrupt flag */
    SPI_INT_FLAG_TXBE       = ((uint32)0x800002), //!< Transmit buffer empty interrupt flag */
    SPI_INT_FLAG_UDR        = ((uint32)0x200008), //!< Underrun flag interrupt flag */
    SPI_INT_FLAG_MME        = ((uint32)0x200020), //!< Master mode error interrupt flag */
    SPI_INT_FLAG_OVR        = ((uint32)0x200040), //!< Receive Overrun interrupt flag */
    SPI_INT_FLAG_FFE        = ((uint32)0x200100)  //!< Frame format error interrupt flag */
} Spi_IntFlagType;

/**@} end of group SPI_Enumerations */
#ifdef __cplusplus
}
#endif

#endif /* SPI_TYPES_H */
/**@} end of group SPI_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
 

