/*!
* @file     system_g32a1085.c
*
* @version  1.0.0
*
* @brief    CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

/* Includes */
#include "g32a1085.h"
#include "Mcu_RcmReg.h"
#include "Mcal.h"
#include "StdRegMacros.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup PLATFORM_Driver
  * @brief PLATFORM driver modules
  @{
*/

/** @defgroup PLATFORM_Macros
  @{
*/

/** Vector Table base offset field. This value must be a multiple of 0x200. */
#define VECT_TAB_OFFSET       0x00

/**@} end of group PLATFORM_Macros */

/** @defgroup PLATFORM_Fuctions
  @{
*/

/*!
* @brief         function used to enable all interrupts
*
* @param[in]     None
* @param[out]    None
* @param[in,out] None
*
*/
void sys_enableAllInterrupts(void)
{
    ResumeAllInterrupts();
}

/*!
* @brief         function used to disable all interrupts
*
* @param[in]     None
* @param[out]    None
* @param[in,out] None
*
*/
void sys_disableAllInterrupts(void)
{
    SuspendAllInterrupts();
}

/*!
* @brief         function used to disable the interrupt number id
*
* @param[in]     id     interrupt id
* @param[out]    None
* @param[in,out] None
*
*/
void sys_disableIsrSource(IRQn_Type id)
{
    NVIC_DisableIRQ(id);
}

/*!
* @brief         function used to enable the interrupt number id and set up the priority
*
* @param[in]     id       interrupt id
* @param[in]     prio     interrupt priority
* @param[out]    None
* @param[in,out] None
*
*/
void sys_enableIsrSource(IRQn_Type id, uint32_t prio)
{
    NVIC_SetPriority(id, prio);
    NVIC_EnableIRQ(id);
}

/*!
* @brief         function used to register the interrupt handler in the interrupt vector
*
* @param[in]     id              interrupt id
* @param[in]     isr_handler     interrupt handle
* @param[out]    None
* @param[in,out] None
*
*/
void sys_registerIsrHandler(IRQn_Type irq_id, uint32_t isr_handler)
{
    REG_WRITE32(SCB->VTOR + ((16 + irq_id) << 2), isr_handler);
}

/*!
* @brief         Setup the microcontroller system
*
* @param[in]     None
* @param[out]    None
* @param[in,out] None
*
*/
void SystemInit(void)
{
    uint32_t reg = 0;

    /* Set HSIEN bit */
    REG_BIT_SET32(RCM_CTRL1_REG_ADDR, RCM_CTRL1_HSIEN_MASK);
    /* Reset SCLKSEL, AHBPSC, APB1PSC, APB2PSC, ADCPSC and COC bits */
    reg = REG_READ32(RCM_CFG1_REG_ADDR);
    REG_WRITE32(RCM_CFG1_REG_ADDR, (reg & (uint32_t)0x08FFB80CU));
    /* Reset HSEEN, CSSEN and PLLEN bits */
    reg = REG_READ32(RCM_CTRL1_REG_ADDR);
    REG_WRITE32(RCM_CTRL1_REG_ADDR, (reg & (uint32_t)0xFEF6FFFFU));
    /* Reset HSEBCFG bit */
    REG_BIT_CLEAR32(RCM_CTRL1_REG_ADDR, RCM_CTRL1_HSEBCFG_MASK);
    /* Reset PLLSRCSEL, PLLHSEPSC, PLLMULCFG bits */
    reg = REG_READ32(RCM_CFG1_REG_ADDR);
    REG_WRITE32(RCM_CFG1_REG_ADDR, (reg & (uint32_t)0xFFC0FFFFU));
    /* Reset PREDIV[3:0] bits */
    reg = REG_READ32(RCM_CFG1_REG_ADDR);
    REG_WRITE32(RCM_CFG1_REG_ADDR, (reg & (uint32_t)0xFFFFFFF0U));
    /* Reset USARTSW[1:0], I2CSW, CECSW and ADCSW bits */
    reg = REG_READ32(RCM_CFG3_REG_ADDR);
    REG_WRITE32(RCM_CFG3_REG_ADDR, (reg & (uint32_t)0xFFFFFEAC));
    /* Reset  HSI14 bit */
    REG_BIT_CLEAR32(RCM_CTRL2_REG_ADDR, RCM_CTRL2_HSI14EN_MASK);
    /* Disable all interrupts */
    REG_WRITE32(RCM_INT1_REG_ADDR, 0U);
    /* Enable Prefetch Buffer */
    REG_BIT_SET32((uint32)0x40022000, (uint32)0x00000010U);
    /* Flash 2 wait state */
    REG_BIT_SET32((uint32)0x40022000, 2U);

#ifdef VECT_TAB_SRAM
    SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET;
#else
    SCB->VTOR = FMC_BASE | VECT_TAB_OFFSET;
#endif
}

/**@} end of group PLATFORM_Fuctions */
/**@} end of group PLATFORM_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */