/*!
* @file     Irme_SmsReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the IRME module
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef IRME_SMS_REG_H
#define IRME_SMS_REG_H

#ifdef __cplusplus
extern "C"{
#endif

#include "Reg_eSys.h"
#include "StdRegMacros.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup IRME_Driver
  * @brief IRME driver modules
  @{
*/

/** @defgroup IRME_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define IRME_SMS_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define IRME_SMS_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define IRME_SMS_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define IRME_SMS_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define IRME_SMS_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define IRME_SMS_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define IRME_SMS_REG_H_SW_PATCH_VERSION                        0x00U

/**@} end of group IRME_Macros */

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Irme_SmsReg.h and Reg_eSys.h */
    #if (IRME_SMS_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Irme_SmsReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Irme_SmsReg.h and Reg_eSys.h */
    #if (IRME_SMS_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Irme_SmsReg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
                                            MACRO DEFINITION
************************************************************************************************************/

/** @defgroup IRME_Macros
  @{
*/
/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SMS_ECC_CFG (Base + 0x04)
************************************************************************************************************/
/** SMS_ECC_CFG register address */
#define SMS_ECC_CFG_REG_ADDR                   ((uint32)(SMS_BASEADDR + (uint32)0x04U))

#define SMS_ECC_CFG_ECC_EN_MASK                ((uint32)0x00000001U)
#define SMS_ECC_CFG_ECC_EN_SHIFT               ((uint8)0U)

#define SMS_ECC_CFG_RD_COR_EN_MASK             ((uint32)0x00000002U)
#define SMS_ECC_CFG_RD_COR_EN_SHIFT            ((uint8)1U)

#define SMS_ECC_CFG_RMW_COR_EN_MASK            ((uint32)0x00000004U)
#define SMS_ECC_CFG_RMW_COR_EN_SHIFT           ((uint8)2U)

#define SMS_ECC_CFG_INSERT_ERR_MASK            ((uint32)0x00000018U)
#define SMS_ECC_CFG_INSERT_ERR_SHIFT           ((uint8)3U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SMS_STAT (Base + 0x08)
************************************************************************************************************/
/** SMS_STAT register address */
#define SMS_STAT_REG_ADDR                      ((uint32)(SMS_BASEADDR + (uint32)0x08U))

#define SMS_STAT_RD_ERR_DET_MASK               ((uint32)0x00000001U)
#define SMS_STAT_RD_ERR_DET_SHIFT              ((uint8)0U)

#define SMS_STAT_RD_ERR_SIN_MASK               ((uint32)0x00000002U)
#define SMS_STAT_RD_ERR_SIN_SHIFT              ((uint8)1U)

#define SMS_STAT_RD_ERR_DBL_MASK               ((uint32)0x00000004U)
#define SMS_STAT_RD_ERR_DBL_SHIFT              ((uint8)2U)

#define SMS_STAT_RMW_ERR_DET_MASK              ((uint32)0x00000008U)
#define SMS_STAT_RMW_ERR_DET_SHIFT             ((uint8)3U)

#define SMS_STAT_RMW_ERR_SIN_MASK              ((uint32)0x00000010U)
#define SMS_STAT_RMW_ERR_SIN_SHIFT             ((uint8)4U)

#define SMS_STAT_RMW_ERR_DBL_MASK              ((uint32)0x00000020U)
#define SMS_STAT_RMW_ERR_DBL_SHIFT             ((uint8)5U)

#define SMS_STAT_IF_INTR_MASK                  ((uint32)0x00010000U)
#define SMS_STAT_IF_INTR_SHIFT                 ((uint8)16U)

/** The SMS_STAT mask bits */
#define EREPM_STS_MASK ((uint32)0x0000003f)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SMS_ECC_LOGn (Base + 0x100)
************************************************************************************************************/
/** SMS_ECC_LOGn register address */
#define SMS_ECC_LOGn_REG_ADDR                  ((uint32)(SMS_BASEADDR + (uint32)0x100U))

#define SMS_ECC_LOGn_ADDR_MASK                 ((uint32)0x000fff80U)
#define SMS_ECC_LOGn_ADDR_SHIFT                ((uint8)7U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SMS_INTRRn (Base + 0x140)
************************************************************************************************************/
/** SMS_STAT register address */
#define SMS_INTRRn_REG_ADDR                    ((uint32)(SMS_BASEADDR + (uint32)0x140U))

#define SMS_INTRRn_RD_ERR_DET_MASK             ((uint32)0x00000001U)
#define SMS_INTRRn_RD_ERR_DET_SHIFT            ((uint8)0U)

#define SMS_INTRRn_RD_ERR_SIN_MASK             ((uint32)0x00000002U)
#define SMS_INTRRn_RD_ERR_SIN_SHIFT            ((uint8)1U)

#define SMS_INTRRn_RD_ERR_DBL_MASK             ((uint32)0x00000004U)
#define SMS_INTRRn_RD_ERR_DBL_SHIFT            ((uint8)2U)

#define SMS_INTRRn_RMW_ERR_DET_MASK            ((uint32)0x00000008U)
#define SMS_INTRRn_RMW_ERR_DET_SHIFT           ((uint8)3U)

#define SMS_INTRRn_RMW_ERR_SIN_MASK            ((uint32)0x00000010U)
#define SMS_INTRRn_RMW_ERR_SIN_SHIFT           ((uint8)4U)

#define SMS_INTRRn_RMW_ERR_DBL_MASK            ((uint32)0x00000020U)
#define SMS_INTRRn_RMW_ERR_DBL_SHIFT           ((uint8)5U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SMS_INTRMn (Base + 0x180)
************************************************************************************************************/
/** SMS_INTRMn register address */
#define SMS_INTRMn_REG_ADDR                    ((uint32)(SMS_BASEADDR + (uint32)0x180U))

#define SMS_INTRMn_RD_ERR_DET_MASK             ((uint32)0x00000001U)
#define SMS_INTRMn_RD_ERR_DET_SHIFT            ((uint8)0U)

#define SMS_INTRMn_RD_ERR_SIN_MASK             ((uint32)0x00000002U)
#define SMS_INTRMn_RD_ERR_SIN_SHIFT            ((uint8)1U)

#define SMS_INTRMn_RD_ERR_DBL_MASK             ((uint32)0x00000004U)
#define SMS_INTRMn_RD_ERR_DBL_SHIFT            ((uint8)2U)

#define SMS_INTRMn_RMW_ERR_DET_MASK            ((uint32)0x00000008U)
#define SMS_INTRMn_RMW_ERR_DET_SHIFT           ((uint8)3U)

#define SMS_INTRMn_RMW_ERR_SIN_MASK            ((uint32)0x00000010U)
#define SMS_INTRMn_RMW_ERR_SIN_SHIFT           ((uint8)4U)

#define SMS_INTRMn_RMW_ERR_DBL_MASK            ((uint32)0x00000020U)
#define SMS_INTRMn_RMW_ERR_DBL_SHIFT           ((uint8)5U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SMS_INTRSn (Base + 0x1C0)
************************************************************************************************************/
/** SMS_INTRSn register address */
#define SMS_INTRSn_REG_ADDR                    ((uint32)(SMS_BASEADDR + (uint32)0x1C0U))

#define SMS_INTRSn_RD_ERR_DET_MASK             ((uint32)0x00000001U)
#define SMS_INTRSn_RD_ERR_DET_SHIFT            ((uint8)0U)

#define SMS_INTRSn_RD_ERR_SIN_MASK             ((uint32)0x00000002U)
#define SMS_INTRSn_RD_ERR_SIN_SHIFT            ((uint8)1U)

#define SMS_INTRSn_RD_ERR_DBL_MASK             ((uint32)0x00000004U)
#define SMS_INTRSn_RD_ERR_DBL_SHIFT            ((uint8)2U)

#define SMS_INTRSn_RMW_ERR_DET_MASK            ((uint32)0x00000008U)
#define SMS_INTRSn_RMW_ERR_DET_SHIFT           ((uint8)3U)

#define SMS_INTRSn_RMW_ERR_SIN_MASK            ((uint32)0x00000010U)
#define SMS_INTRSn_RMW_ERR_SIN_SHIFT           ((uint8)4U)

#define SMS_INTRSn_RMW_ERR_DBL_MASK            ((uint32)0x00000020U)
#define SMS_INTRSn_RMW_ERR_DBL_SHIFT           ((uint8)5U)

/**@} end of group IRME_Macros */

#ifdef __cplusplus
}
#endif

#endif

/**@} end of group IRME_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
