/*!
* @file     Pdl_DmaReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the DMA module.
*           This header file includes the register definitions of the DMA module.
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef PDL_DMA_REG_H
#define PDL_DMA_REG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"
/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup PDL_Driver
  * @brief PDL driver modules
  @{
*/

/** @defgroup PDL_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define PDL_DMA_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define PDL_DMA_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PDL_DMA_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PDL_DMA_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define PDL_DMA_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PDL_DMA_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PDL_DMA_REG_H_SW_PATCH_VERSION                        0x00U

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Pdl_DmaReg.h and Reg_eSys.h */
    #if (PDL_DMA_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Pdl_DmaReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Pdl_DmaReg.h and Reg_eSys.h */
    #if (PDL_DMA_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Pdl_DmaReg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DMA_INTSTS (Base + 0x00)
************************************************************************************************************/
/** DMA_INTSTS register address */
#define DMA_INTSTS_REG_ADDR              ((uint32)(DMA_BASEADDR + (uint32)0x00U))

/** Note: The value of ChId can be 1, 2, 3, 4, 5. */
#define DMA_CH_GINTFLG_MASK(ChId)        ((uint32)((uint32)1U << (((uint32)ChId - (uint32)1U) * (uint32)4U)))
#define DMA_CH_GINTFLG_SHIFT(ChId)       ((uint8)((ChId - 1U) * 4U + 0U))

#define DMA_CH_TCFLG_MASK(ChId)          ((uint32)((uint32)2U << (((uint32)ChId - (uint32)1U) * (uint32)4U)))
#define DMA_CH_TCFLG_SHIFT(ChId)         ((uint8)((ChId - 1U) * 4U + 1U))

#define DMA_CH_HTFLG_MASK(ChId)          ((uint32)((uint32)4U << (((uint32)ChId - (uint32)1U) * (uint32)4U)))
#define DMA_CH_HTFLG_SHIFT(ChId)         ((uint8)((ChId - 1U) * 4U + 2U))

#define DMA_CH_TERRFLG_MASK(ChId)        ((uint32)((uint32)8U << (((uint32)ChId - (uint32)1U) * (uint32)4U)))
#define DMA_CH_TERRFLG_SHIFT(ChId)       ((uint8)((ChId - 1U) * 4U + 3U))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DMA_INTFCLR (Base + 0x04)
************************************************************************************************************/
/** DMA_INTFCLR register address */
#define DMA_INTFCLR_REG_ADDR             ((uint32)(DMA_BASEADDR + (uint32)0x04U))

/** Note: The value of ChId can be 1, 2, 3, 4, 5. */
#define DMA_CH_GINTCLR_MASK(ChId)        ((uint32)((uint32)1U << (((uint32)ChId - (uint32)1U) * (uint32)4U)))
#define DMA_CH_GINTCLR_SHIFT(ChId)       ((uint8)((ChId - 1U) * 4U + 0U))

#define DMA_CH_TCCLR_MASK(ChId)          ((uint32)((uint32)2U << (((uint32)ChId - (uint32)1U) * (uint32)4U)))
#define DMA_CH_TCCLR_SHIFT(ChId)         ((uint8)((ChId - 1U) * 4U + 1U))

#define DMA_CH_HTCLR_MASK(ChId)          ((uint32)((uint32)4U << (((uint32)ChId - (uint32)1U) * (uint32)4U)))
#define DMA_CH_HTCLR_SHIFT(ChId)         ((uint8)((ChId - 1U) * 4U + 2U))

#define DMA_CH_TERRCLR_MASK(ChId)        ((uint32)((uint32)8U << (((uint32)ChId - (uint32)1U) * (uint32)4U)))
#define DMA_CH_TERRCLR_SHIFT(ChId)       ((uint8)((ChId - 1U) * 4U + 3U))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DMA_CHCFG(ChId) (Base + 0x08U + 20U * (ChId - 1))
************************************************************************************************************/
/** DMA_CHCFG(ChId) register address */
#define DMA_CHCFG_REG_ADDR(ChId)         ((uint32)((uint32)DMA_BASEADDR + 0x08U + (20U * (((uint32)(ChId)) - 1U))))

#define DMA_CHCFG_CHEN_MASK              ((uint32)0x00000001U)
#define DMA_CHCFG_CHEN_SHIFT             ((uint8)0U)

#define DMA_CHCFG_TCINTEN_MASK           ((uint32)0x00000002U)
#define DMA_CHCFG_TCINTEN_SHIFT          ((uint8)1U)

#define DMA_CHCFG_HTINTEN_MASK           ((uint32)0x00000004U)
#define DMA_CHCFG_HTINTEN_SHIFT          ((uint8)2U)

#define DMA_CHCFG_TERRINTEN_MASK         ((uint32)0x00000008U)
#define DMA_CHCFG_TERRINTEN_SHIFT        ((uint8)3U)

#define DMA_CHCFG_DIRCFG_MASK            ((uint32)0x00000010U)
#define DMA_CHCFG_DIRCFG_SHIFT           ((uint8)4U)

#define DMA_CHCFG_CIRMODE_MASK           ((uint32)0x00000020U)
#define DMA_CHCFG_CIRMODE_SHIFT          ((uint8)5U)

#define DMA_CHCFG_PERIMODE_MASK          ((uint32)0x00000040U)
#define DMA_CHCFG_PERIMODE_SHIFT         ((uint8)6U)

#define DMA_CHCFG_MIMODE_MASK            ((uint32)0x00000080U)
#define DMA_CHCFG_MIMODE_SHIFT           ((uint8)7U)

#define DMA_CHCFG_PERSIZE_MASK           ((uint32)0x00000300U)
#define DMA_CHCFG_PERSIZE_SHIFT          ((uint8)8U)

#define DMA_CHCFG_MSIZE_MASK             ((uint32)0x00000C00U)
#define DMA_CHCFG_MSIZE_SHIFT            ((uint8)10U)

#define DMA_CHCFG_CHPL_MASK              ((uint32)0x00003000U)
#define DMA_CHCFG_CHPL_SHIFT             ((uint8)12U)

#define DMA_CHCFG_M2MMODE_MASK           ((uint32)0x00004000U)
#define DMA_CHCFG_M2MMODE_SHIFT          ((uint8)14U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DMA_CHNDATA(ChId) (Base + 0x0CU + 20U * (ChId - 1))
************************************************************************************************************/
/** DMA_CHNDATA(ChId) register address */
#define DMA_CHNDATA_REG_ADDR(ChId)       ((uint32)((uint32)DMA_BASEADDR + 0x0CU + (20U * (((uint32)(ChId)) - 1U))))

#define DMA_CHNDATA_NDATAT_MASK          ((uint32)0x0000FFFFU)
#define DMA_CHNDATA_NDATAT_SHIFT         ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DMA_CHPADDR(ChId) (Base + 0x10U + 20U * (ChId - 1))
************************************************************************************************************/
/** DMA_CHPADDR(ChId) register address */
#define DMA_CHPADDR_REG_ADDR(ChId)       ((uint32)((uint32)DMA_BASEADDR + 0x10U + (20U * (((uint32)(ChId)) - 1U))))

#define DMA_CHPADDR_PERADDR_MASK         ((uint32)0xFFFFFFFFU)
#define DMA_CHPADDR_PERADDR_SHIFT        ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DMA_CHMADDR(ChId) (Base + 0x14U + 20U * (ChId - 1))
************************************************************************************************************/
/** DMA_CHMADDR(ChId) register address */
#define DMA_CHMADDR_REG_ADDR(ChId)       ((uint32)((uint32)DMA_BASEADDR + 0x14U + (20U * (((uint32)(ChId)) - 1U))))

#define DMA_CHMADDR_MEMADDR_MASK         ((uint32)0xFFFFFFFFU)
#define DMA_CHMADDR_MEMADDR_SHIFT        ((uint8)0U)

/**@} end of group PDL_Macros */
#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* PDL_DMA_REG_H */
/**@} end of group PDL_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
