/*!
* @file     Pdl_DmaTypes.h
*
* @version  1.0.0
*
* @brief    Data Type Definition File for the PDL Module Based on DMA IP.
*           
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef PDL_DMA_TYPES_H
#define PDL_DMA_TYPES_H

#ifdef __cplusplus
extern "C" {
#endif /* ifdef __cplusplus */

#include "Std_Types.h"
#include "StdRegMacros.h"
#include "CDD_Pdl_Cfg.h"
#include "SchM_Pdl.h"
 
/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup PDL_Driver
  * @brief PDL driver modules
  @{
*/

/** @defgroup PDL_Macros
  @{
*/
/***********************************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
***********************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define PDL_DMA_TYPES_H_VENDOR_ID                          0x00C1U
/** Module ID of this module, as defined in the BSW Module List. */
#define PDL_DMA_TYPES_H_MODULE_ID                          0x00FFU
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PDL_DMA_TYPES_H_AR_RELEASE_MAJOR_VERSION           0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PDL_DMA_TYPES_H_AR_RELEASE_MINOR_VERSION           0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PDL_DMA_TYPES_H_AR_RELEASE_REVISION_VERSION        0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PDL_DMA_TYPES_H_SW_MAJOR_VERSION                   0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PDL_DMA_TYPES_H_SW_MINOR_VERSION                   0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PDL_DMA_TYPES_H_SW_PATCH_VERSION                   0x00U

/**********************************************************************************************************************
                                  VERSION INFOMATION VERIFICATION
***********************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Pdl_DmaTypes.h and Std_Types.h */
    #if (PDL_DMA_TYPES_H_AR_RELEASE_MAJOR_VERSION != STD_TYPES_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Pdl_DmaTypes.h and Std_Types.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Pdl_DmaTypes.h and Std_Types.h */
    #if (PDL_DMA_TYPES_H_AR_RELEASE_MINOR_VERSION != STD_TYPES_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Pdl_DmaTypes.h and Std_Types.h"
    #endif

    /* Make sure the AUTOSAR major version number is the same between Pdl_DmaTypes.h and StdRegMacros.h */
    #if (PDL_DMA_TYPES_H_AR_RELEASE_MAJOR_VERSION != STD_REG_MACROS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Pdl_DmaTypes.h and StdRegMacros.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Pdl_DmaTypes.h and StdRegMacros.h */
    #if (PDL_DMA_TYPES_H_AR_RELEASE_MINOR_VERSION != STD_REG_MACROS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Pdl_DmaTypes.h and StdRegMacros.h"
    #endif
#endif

/**********************************************************************************************************************
                                            MACRO DEFINITION
***********************************************************************************************************************/
#define DMA_MODULE_EN                       (1U)
#define DMA_MODULE_DIS                      (0U)
/** Number of DMA channels per module */
#define DMA_CHS_PER_MODULE                  (5U) 

/** Dma error type */
#define DMA_CH_NO_ERR                       ((Pdl_DmaChErrStsType)0x00U)
#define DMA_UNRECOG_ERR                     ((Pdl_DmaChErrStsType)0x01U)

/** When getting the DMA error status,the define is used when no channel should be reported */
#define PDL_DMA_CH_NO_CONFIG                (0xFFU)

/** Dma Notification type */
#define PDL_DMA_TRAN_COMPLETED              ((Pdl_DmaTranNotifType)0U)
#define PDL_DMA_TRAN_HALF_COMPLETED         ((Pdl_DmaTranNotifType)1U)
#define PDL_DMA_TRAN_ERROR                  ((Pdl_DmaTranNotifType)2U)

/** DMA channel intrrupts enable/disable */
#define DMA_CH_TC_INT_ENABLE                (1U << DMA_CHCFG_TCINTEN_SHIFT) 
#define DMA_CH_TC_INT_DISABLE               (0U << DMA_CHCFG_TCINTEN_SHIFT)

/** Enable DMA channel half transfer interrupts */
#define DMA_CH_HT_INT_ENABLE                (1U << DMA_CHCFG_HTINTEN_SHIFT) 
/** Disable DMA channel half transfer interrupts */
#define DMA_CH_HT_INT_DISABLE               (0U << DMA_CHCFG_HTINTEN_SHIFT) 

/** Enable DMA channel transfer error interrupts */
#define DMA_CH_TE_INT_ENABLE                (1U << DMA_CHCFG_TERRINTEN_SHIFT) 
/** Disable DMA channel transfer error interrupts */
#define DMA_CH_TE_INT_DISABLE               (0U << DMA_CHCFG_TERRINTEN_SHIFT) 

/** DMA1 Channel 1 */
#define DMA_HW_CH1                          (1U) 
/** DMA1 Channel 2 */
#define DMA_HW_CH2                          (2U) 
/** DMA1 Channel 3 */
#define DMA_HW_CH3                          (3U) 
/** DMA1 Channel 4 */
#define DMA_HW_CH4                          (4U) 
/** DMA1 Channel 5 */
#define DMA_HW_CH5                          (5U) 
/**@} end of group PDL_Macros */
/**********************************************************************************************************************
                                             ENUMERATION DEFINITION
***********************************************************************************************************************/
/** @defgroup PDL_Enumerations
  @{
*/
#if (STD_ON == CDD_PDL_DMA_SUPPORT)
/**
 * @brief    PDL BIT State
 */
typedef enum
{
    PDL_BIT_RESET = 0U,
    PDL_BIT_SET
} Pdl_BitStatusType;

/**
 * @brief   DMA data transfer direction
 */
typedef enum
{
    DMA_DIR_PERIPHERAL = ((uint8)0), //!< Peripheral to memory 
    DMA_DIR_MEMORY = ((uint8)1)      //!< Memory to peripheral 
} Pdl_DmaDirType;

/**
 * @brief   DMA peripheral increment mode
 */
typedef enum
{
    DMA_PERIPHERAL_INC_DISABLE = ((uint8)0), //!< Disable peripheral address increment mode 
    DMA_PERIPHERAL_INC_ENABLE = ((uint8)1)   //!< Enable peripheral address increment mode 
} Pdl_DmaPeripheralIncType;

/**
 * @brief   DMA memory increment mode
 */
typedef enum
{
    DMA_MEMORY_INC_DISABLE = ((uint8)0), //!< Disable memory address increment mode 
    DMA_MEMORY_INC_ENABLE = ((uint8)1)   //!< Enable memory address increment mode 
} Pdl_DmaMemIncType;

/**
 * @brief   DMA peripheral data size
 */
typedef enum
{
    DMA_PERIPHERAL_DATASIZE_BYTE = ((uint8)0x00),     //!< Set peripheral data size to byte 
    DMA_PERIPHERAL_DATASIZE_HALFWORD = ((uint8)0x01), //!< Set peripheral data size to half-word 
    DMA_PERIPHERAL_DATASIZE_WORD = ((uint8)0x02)      //!< Set peripheral data size to word 
} Pdl_DmaPeriDataSizeType;

/**
 * @brief   DMA memory data size
 */
typedef enum
{
    DMA_MEMORY_DATASIZE_BYTE = ((uint8)0x00),     //!< Set memory data size to byte 
    DMA_MEMORY_DATASIZE_HALFWORD = ((uint8)0x01), //!< Set memory data size to half-word 
    DMA_MEMORY_DATASIZE_WORD = ((uint8)0x02)      //!< Set memory data size to word 
} Pdl_DmaMemDataSizeType;

/**
 * @brief   DMA circular mode
 */
typedef enum
{
    DMA_CIRCULAR_DISABLE = ((uint8)0), //!< Disable circular mode 
    DMA_CIRCULAR_ENABLE = ((uint8)1)   //!< Enable circular mode 
} Pdl_DmaCircEnStsType;

/**
 * @brief   DMA priority level
 */
typedef enum
{
    DMA_PRIORITY_LEVEL_LOW = ((uint8)0x00),     //!< Set priority level to low 
    DMA_PRIORITY_LEVEL_MEDIUM = ((uint8)0x01),  //!< Set priority level to medium 
    DMA_PRIORITY_LEVEL_HIGHT = ((uint8)0x02),   //!< Set priority level to high 
    DMA_PRIORITY_LEVEL_VERYHIGH = ((uint8)0x03) //!< Set priority level to very high 
} Pdl_DmaProLevType;

/**
 * @brief   DMA memory to memory
 */
typedef enum
{
    DMA_M2M_DISABLE = ((uint8)0), //!< Disable memory to memory mode 
    DMA_M2M_ENABLE = ((uint8)1)   //!< Enable memory to memory mode 
} Pdl_DmaM2mEnStsType;

/**
 * @brief    DMA flag definition
 */
typedef enum
{
    DMA1_FLAG_AL1 = ((uint32)0x00000001), //!< Channel 1 All flag 
    DMA1_FLAG_TF1 = ((uint32)0X00000002), //!< Channel 1 Transfer Complete flag 
    DMA1_FLAG_HT1 = ((uint32)0X00000004), //!< Channel 1 Half Transfer Complete flag 
    DMA1_FLAG_TE1 = ((uint32)0X00000008), //!< Channel 1 Transfer Error flag 

    DMA1_FLAG_AL2 = ((uint32)0x00000010), //!< Channel 2 All flag 
    DMA1_FLAG_TF2 = ((uint32)0x00000020), //!< Channel 2 Transfer Complete flag 
    DMA1_FLAG_HT2 = ((uint32)0x00000040), //!< Channel 2 Half Transfer Complete flag 
    DMA1_FLAG_TE2 = ((uint32)0x00000080), //!< Channel 2 Transfer Error flag 

    DMA1_FLAG_AL3 = ((uint32)0x00000100), //!< Channel 3 All flag 
    DMA1_FLAG_TF3 = ((uint32)0x00000200), //!< Channel 3 Transfer Complete flag 
    DMA1_FLAG_HT3 = ((uint32)0x00000400), //!< Channel 3 Half Transfer Complete flag 
    DMA1_FLAG_TE3 = ((uint32)0x00000800), //!< Channel 3 Transfer Error flag 

    DMA1_FLAG_AL4 = ((uint32)0x00001000), //!< Channel 4 All flag 
    DMA1_FLAG_TF4 = ((uint32)0x00002000), //!< Channel 4 Transfer Complete flag 
    DMA1_FLAG_HT4 = ((uint32)0x00004000), //!< Channel 4 Half Transfer Complete flag 
    DMA1_FLAG_TE4 = ((uint32)0x00008000), //!< Channel 4 Transfer Error flag 

    DMA1_FLAG_AL5 = ((uint32)0x00010000), //!< Channel 5 All flag 
    DMA1_FLAG_TF5 = ((uint32)0x00020000), //!< Channel 5 Transfer Complete flag 
    DMA1_FLAG_HT5 = ((uint32)0x00040000), //!< Channel 5 Half Transfer Complete flag 
    DMA1_FLAG_TE5 = ((uint32)0x00080000)  //!< Channel 5 Transfer Error flag 
} Pdl_DmaChFlagType;

/**
 * @brief    DMA interrupt flag definition
 */
typedef enum
{
    DMA1_INT_FLAG_AL1 = ((uint32)0x00000001), //!< Channel 1 All interrupt flag 
    DMA1_INT_FLAG_TF1 = ((uint32)0x00000002), //!< Channel 1 Transfer Complete interrupt flag 
    DMA1_INT_FLAG_HT1 = ((uint32)0x00000004), //!< Channel 1 Half Transfer Complete interrupt flag 
    DMA1_INT_FLAG_TE1 = ((uint32)0x00000008), //!< Channel 1 Transfer Error interrupt flag 

    DMA1_INT_FLAG_AL2 = ((uint32)0x00000010), //!< Channel 2 All interrupt flag 
    DMA1_INT_FLAG_TF2 = ((uint32)0x00000020), //!< Channel 2 Transfer Complete interrupt flag 
    DMA1_INT_FLAG_HT2 = ((uint32)0x00000040), //!< Channel 2 Half Transfer Complete interrupt flag 
    DMA1_INT_FLAG_TE2 = ((uint32)0x00000080), //!< Channel 2 Transfer Error interrupt flag 

    DMA1_INT_FLAG_AL3 = ((uint32)0x00000100), //!< Channel 3 All interrupt flag 
    DMA1_INT_FLAG_TF3 = ((uint32)0x00000200), //!< Channel 3 Transfer Complete interrupt flag 
    DMA1_INT_FLAG_HT3 = ((uint32)0x00000400), //!< Channel 3 Half Transfer Complete interrupt flag 
    DMA1_INT_FLAG_TE3 = ((uint32)0x00000800), //!< Channel 3 Transfer Error interrupt flag 

    DMA1_INT_FLAG_AL4 = ((uint32)0x00001000), //!< Channel 4 All interrupt flag 
    DMA1_INT_FLAG_TF4 = ((uint32)0x00002000), //!< Channel 4 Transfer Complete interrupt flag 
    DMA1_INT_FLAG_HT4 = ((uint32)0x00004000), //!< Channel 4 Half Transfer Complete interrupt flag 
    DMA1_INT_FLAG_TE4 = ((uint32)0x00008000), //!< Channel 4 Transfer Error interrupt flag 

    DMA1_INT_FLAG_AL5 = ((uint32)0x00010000), //!< Channel 5 All interrupt flag 
    DMA1_INT_FLAG_TF5 = ((uint32)0x00020000), //!< Channel 5 Transfer Complete interrupt flag 
    DMA1_INT_FLAG_HT5 = ((uint32)0x00040000), //!< Channel 5 Half Transfer Complete interrupt flag 
    DMA1_INT_FLAG_TE5 = ((uint32)0x00080000)  //!< Channel 5 Transfer Error interrupt flag 
} Pdl_DmaIntFlagType;

/**
 * @brief   DMA interrupt source
 */
typedef enum
{
    DMA_INT_TFIE = BIT1, //!< Transfer complete interrupt enable 
    DMA_INT_HTIE = BIT2, //!< Half Transfer interrupt enable 
    DMA_INT_TEIE = BIT3  //!< Transfer error interrupt enable 
} Pdl_DmaIntType;
/**@} end of group PDL_Enumerations */
/**********************************************************************************************************************
                                                 OTHER TYPE DEFINITION
***********************************************************************************************************************/
/** @defgroup PDL_Typedef
  @{
*/
/** The DMA instance id type */
typedef uint8 Pdl_DmaModType;

/** The error channel type */
typedef uint16 Pdl_DmaErrChType;

typedef uint8 Pdl_DmaChType;

/** Dma notification type */
typedef uint8 Pdl_DmaTranNotifType;

/** The type of the DMA channel priority */
typedef uint8 Pdl_DmaPrioType;

/** The configuration  type of DMA_CTRL register */
typedef uint8 Pdl_DmaCtrlType;

/** Dma transfer size type */
typedef uint8 Pdl_DmaTranSizeType;

/** The DMA enabled information type(whether DMA is enabled in configuration or not) */
typedef uint8 Pdl_DmaEnStsType;

/** Pdl DMA error type */
typedef uint8 Pdl_DmaChErrStsType;

/**  The Dma request type */
typedef uint8 Pdl_DmaReqType;

#if (STD_ON == CDD_PDL_DMA_SUPPORT)
typedef void       (*Pdl_NotifyType)(void);
typedef uint8      Pdl_ChType;
#endif  /* {if (STD_ON == CDD_PDL_DMA_SUPPORT)} */

#if(STD_ON == CDD_PDL_DMA_ERR_NOTIFICATION_SUPPORT)
    /** The type of error notification */
    typedef void (*Pdl_DmaErrNotifiType)(void);
#endif

/**@} end of group PDL_Typedef */
/** @defgroup PDL_Structure
  @{
*/
/**
 * @brief   DMA channel config struct definition
 */
typedef struct
{
    uint32 memAddr; //!< Specifies the DMA memory base address 
    uint32 periphAddr; //!< Specifies the DMA peripheral base address 
    Pdl_DmaDirType dir; //!< Specifies the DMA data transfer direction 
    uint32 bufSize; //!< Specifies the DMA buffer size 
    Pdl_DmaMemDataSizeType memDataWidth; //!< Specifies the DMA memory data size 
    Pdl_DmaPeriDataSizeType periphDataWidth; //!< Specifies the DMA peripheral data size 
    Pdl_DmaMemIncType memInc; //!< Specifies the DMA memory address increment 
    Pdl_DmaPeripheralIncType periphInc; //!< Specifies the DMA peripheral address increment 
    Pdl_DmaCircEnStsType circularMode; //!< Specifies the DMA circular mode 
    Pdl_DmaProLevType priority; //!< Specifies the DMA software priority 
    Pdl_DmaM2mEnStsType mem2Mem; //!< Specifies the DMA memory-to-memory transfer 
} Pdl_DmaChHwConfigType;

/**
 * @brief   The error structure
 */
typedef struct
{
    Pdl_DmaErrChType     errCh;
    Pdl_DmaChErrStsType  errId;
} Pdl_DmaGlobErrStsType;

typedef struct
{
    CONST(Pdl_DmaCtrlType, PDL_CONST)  dmaChIntCtrl;
    CONST(Pdl_DmaChType, PDL_CONST) dmaChannel;
#if (STD_ON == CDD_PDL_DMA_NOTIFICATION_ENABLE)
    CONST(Pdl_NotifyType, PDL_CONST) dmaChNotifiFuncPtr;
#endif /* {if (STD_ON == CDD_PDL_DMA_NOTIFICATION_ENABLE)} */
#if (STD_ON == CDD_PDL_DMA_ERR_NOTIFICATION_SUPPORT)
    CONST(Pdl_DmaErrNotifiType, PDL_CONST) dmaErrNotifiPtr; //!< The pointer of the notification function 
#endif /* {if (STD_ON == CDD_PDL_DMA_ERR_NOTIFICATION_SUPPORT)} */
} Pdl_DmaChConfigType;

typedef struct
{
    CONST(Pdl_DmaChType, PDL_CONST)   dmaChCnt;
    CONST(Pdl_DmaChConfigType, PDL_CONST) (*const chConfigPtr)[];
} Pdl_DmaConfigType;

#endif /* {if (STD_ON == CDD_PDL_DMA_SUPPORT)} */

/**@} end of group PDL_Structure */
#ifdef __cplusplus
}
#endif /* ifdef __cplusplus */

#endif /* PDL_DMA_TYPES_H */
/**@} end of group PDL_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */

