/*!
* @file     Icu_EintReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the external interrupt(EINT) module
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef ICU_EINT_REG_H
#define ICU_EINT_REG_H

#ifdef __cplusplus
extern "C"{
#endif

#include "Reg_eSys.h"
#include "Compiler.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup ICU_Driver
  * @brief ICU driver modules
  @{
*/

/** @defgroup ICU_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define ICU_EINT_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define ICU_EINT_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define ICU_EINT_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define ICU_EINT_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define ICU_EINT_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define ICU_EINT_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define ICU_EINT_REG_H_SW_PATCH_VERSION                        0x00U

/**@} end of group ICU_Macros */

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Icu_EintReg.h and Reg_eSys.h */
    #if (ICU_EINT_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Icu_EintReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Icu_EintReg.h and Reg_eSys.h */
    #if (ICU_EINT_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Icu_EintReg.h and Reg_eSys.h"
    #endif
#endif

/** @defgroup ICU_Macros
  @{
*/
/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: EINT_IMASK (Base + 0x00)
************************************************************************************************************/
/** EINT_IMASK register address */
#define EINT_IMASK_REG_ADDR              ((uint32)(EINT_BASEADDR + (uint32)0x00U))

#define EINT_IMASK_MASK                  ((uint32)0x0FFFFFFFU)
#define EINT_IMASK_SHIFT                 ((uint8)0U)

#define EINT_IMASK_SET(BIT)              ((uint32)(1U << BIT))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: EINT_EMASK (Base + 0x04)
************************************************************************************************************/
/** EINT_EMASK register address */
#define EINT_EMASK_REG_ADDR              ((uint32)(EINT_BASEADDR + (uint32)0x04U))

#define EINT_EMASK_MASK                  ((uint32)0x0FFFFFFFU)
#define EINT_EMASK_SHIFT                 ((uint8)0U)

#define EINT_EMASK_SET(BIT)              ((uint32)(1U << BIT))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: EINT_RTEN (Base + 0x08)
************************************************************************************************************/
/** EINT_RTEN register address */
#define EINT_RTEN_REG_ADDR               ((uint32)(EINT_BASEADDR + (uint32)0x08U))

#define EINT_RTEN_MASK                   ((uint32)0x0001FFFFU)
#define EINT_RTEN_SHIFT                  ((uint8)0U)

#define EINT_RTEN_SET(BIT)               ((uint32)(1U << BIT))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: EINT_FTEN (Base + 0x0C)
************************************************************************************************************/
/** EINT_FTEN register address */
#define EINT_FTEN_REG_ADDR               ((uint32)(EINT_BASEADDR + (uint32)0x0CU))

#define EINT_FTEN_MASK                   ((uint32)0x0001FFFFU)
#define EINT_FTEN_SHIFT                  ((uint8)0U)

#define EINT_FTEN_SET(BIT)               ((uint32)(1U << BIT))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: EINT_SWINTE (Base + 0x10)
************************************************************************************************************/
/** EINT_SWINTE register address */
#define EINT_SWINTE_REG_ADDR             ((uint32)(EINT_BASEADDR + (uint32)0x10U))

#define EINT_SWINTE_MASK                 ((uint32)0x0001FFFFU)
#define EINT_SWINTE_SHIFT                ((uint8)0U)

#define EINT_SWINTE_SET(BIT)             ((uint32)(1U << BIT))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: EINT_IPEND (Base + 0x14)
************************************************************************************************************/
/** EINT_IPEND register address */
#define EINT_IPEND_REG_ADDR              ((uint32)(EINT_BASEADDR + (uint32)0x14U))

#define EINT_IPEND_MASK                  ((uint32)0x0001FFFFU)
#define EINT_IPEND_SHIFT                 ((uint8)0U)

#define EINT_IPEND_SET(BIT)              ((uint32)(1U << BIT))

/**@} end of group ICU_Macros */

#ifdef __cplusplus
}
#endif

#endif

/**@} end of group ICU_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
