/*!
* @file     Mcu_PmuReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the Power Management Unit(PMU) module.
*
* @details  This header file includes the register definitions of the Power Management Unit(PMU) module.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef MCU_PMUREG_H
#define MCU_PMUREG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @addtogroup MCU_Driver
  @{
*/

/** @defgroup MCU_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define MCU_PMU_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define MCU_PMU_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_PMU_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_PMU_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_PMU_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_PMU_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_PMU_REG_H_SW_PATCH_VERSION                        0x00U

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Mcu_PmuReg.h and Reg_eSys.h */
    #if (MCU_PMU_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Mcu_PmuReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Mcu_PmuReg.h and Reg_eSys.h */
    #if (MCU_PMU_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Mcu_PmuReg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: PMU_CTRL (Base + 0x00)
************************************************************************************************************/
/** PMU_CTRL register address */
#define PMU_CTRL_REG_ADDR                ((uint32)(PMU_BASEADDR + (uint32)0x00U))

#define PMU_CTRL_LPDSCFG_MASK            ((uint32)0x00000001U)
#define PMU_CTRL_LPDSCFG_SHIFT           ((uint8)0U)

#define PMU_CTRL_PDDSCFG_MASK            ((uint32)0x00000002U)
#define PMU_CTRL_PDDSCFG_SHIFT           ((uint8)1U)

#define PMU_CTRL_WUFLGCLR_MASK           ((uint32)0x00000004U)
#define PMU_CTRL_WUFLGCLR_SHIFT          ((uint8)2U)

#define PMU_CTRL_SBFLGCLR_MASK           ((uint32)0x00000008U)
#define PMU_CTRL_SBFLGCLR_SHIFT          ((uint8)3U)

#define PMU_CTRL_PVDEN_MASK              ((uint32)0x00000010U)
#define PMU_CTRL_PVDEN_SHIFT             ((uint8)4U)

#define PMU_CTRL_PLSEL_MASK              ((uint32)0x000000E0U)
#define PMU_CTRL_PLSEL_SHIFT             ((uint8)5U)

#define PMU_CTRL_BPWEN_MASK              ((uint32)0x00000100U)
#define PMU_CTRL_BPWEN_SHIFT             ((uint8)8U)

#define PMU_CTRL_STOP_FILTER_EN_MASK     ((uint32)0x00000200U)
#define PMU_CTRL_STOP_FILTER_EN_SHIFT    ((uint8)9U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: PMU_CSTS (Base + 0x04)
************************************************************************************************************/
/** PMU_CSTS register address */
#define PMU_CSTS_REG_ADDR                ((uint32)(PMU_BASEADDR + (uint32)0x04U))

#define PMU_CSTS_WUEFLG_MASK             ((uint32)0x00000001U)
#define PMU_CSTS_WUEFLG_SHIFT            ((uint8)0U)

#define PMU_CSTS_SBFLG_MASK              ((uint32)0x00000002U)
#define PMU_CSTS_SBFLG_SHIFT             ((uint8)1U)

#define PMU_CSTS_PVDOFLG_MASK            ((uint32)0x00000004U)
#define PMU_CSTS_PVDOFLG_SHIFT           ((uint8)2U)

/**@} end of group MCU_Macros */

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* MCU_PMU_REG_H */

/**@} end of group MCU_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
