/*!
* @file     Pdl_TmrReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the timer module.
*           This header file includes the register definitions of the timer module.
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef PDL_TMR_REG_H
#define PDL_TMR_REG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"
/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup PDL_Driver
  * @brief PDL driver modules
  @{
*/

/** @defgroup PDL_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define PDL_TMR_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define PDL_TMR_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PDL_TMR_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PDL_TMR_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PDL_TMR_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PDL_TMR_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PDL_TMR_REG_H_SW_PATCH_VERSION                        0x00U

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Pdl_TmrReg.h and Reg_eSys.h */
    #if (PDL_TMR_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Pdl_TmrReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Pdl_TmrReg.h and Reg_eSys.h */
    #if (PDL_TMR_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Pdl_TmrReg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CTRL1(Base + 0x00)
************************************************************************************************************/
/** TMRx_CTRL1 register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CTRL1_REG_ADDR(ModId)        ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x00U))

#define TMR_CTRL1_CNTEN_MASK             ((uint32)0x00000001U)
#define TMR_CTRL1_CNTEN_SHIFT            ((uint8)0U)

#define TMR_CTRL1_UD_MASK                ((uint32)0x00000002U)
#define TMR_CTRL1_UD_SHIFT               ((uint8)1U)

#define TMR_CTRL1_URSSEL_MASK            ((uint32)0x00000004U)
#define TMR_CTRL1_URSSEL_SHIFT           ((uint8)2U)

#define TMR_CTRL1_SPMEN_MASK             ((uint32)0x00000008U)
#define TMR_CTRL1_SPMEN_SHIFT            ((uint8)3U)

#define TMR_CTRL1_CNTDIR_MASK            ((uint32)0x00000010U)
#define TMR_CTRL1_CNTDIR_SHIFT           ((uint8)4U)

#define TMR_CTRL1_CAMSEL_MASK            ((uint32)0x00000060U)
#define TMR_CTRL1_CAMSEL_SHIFT           ((uint8)5U)

#define TMR_CTRL1_ARPEN_MASK             ((uint32)0x00000080U)
#define TMR_CTRL1_ARPEN_SHIFT            ((uint8)7U)

#define TMR_CTRL1_CLKDIV_MASK            ((uint32)0x00000300U)
#define TMR_CTRL1_CLKDIV_SHIFT           ((uint8)8U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CTRL2(Base + 0x04)
************************************************************************************************************/
/** TMRx_CTRL2 register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CTRL2_REG_ADDR(ModId)        ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x04U))

#define TMR_CTRL2_CCPEN_MASK             ((uint32)0x00000001U)
#define TMR_CTRL2_CCPEN_SHIFT            ((uint8)0U)

#define TMR_CTRL2_CCUSEL_MASK            ((uint32)0x00000004U)
#define TMR_CTRL2_CCUSEL_SHIFT           ((uint8)2U)

#define TMR_CTRL2_CCDSEL_MASK            ((uint32)0x00000008U)
#define TMR_CTRL2_CCDSEL_SHIFT           ((uint8)3U)

#define TMR_CTRL2_MMSEL_MASK             ((uint32)0x00000070U)
#define TMR_CTRL2_MMSEL_SHIFT            ((uint8)4U)

#define TMR_CTRL2_TI1SEL_MASK            ((uint32)0x00000080U)
#define TMR_CTRL2_TI1SEL_SHIFT           ((uint8)7U)

#define TMR_CTRL2_OC1OIS_MASK            ((uint32)0x00000100U)
#define TMR_CTRL2_OC1OIS_SHIFT           ((uint8)8U)

#define TMR_CTRL2_OC1NOIS_MASK           ((uint32)0x00000200U)
#define TMR_CTRL2_OC1NOIS_SHIFT          ((uint8)9U)

#define TMR_CTRL2_OC2OIS_MASK            ((uint32)0x00000400U)
#define TMR_CTRL2_OC2OIS_SHIFT           ((uint8)10U)

#define TMR_CTRL2_OC2NOIS_MASK           ((uint32)0x00000800U)
#define TMR_CTRL2_OC2NOIS_SHIFT          ((uint8)11U)

#define TMR_CTRL2_OC3OIS_MASK            ((uint32)0x00001000U)
#define TMR_CTRL2_OC3OIS_SHIFT           ((uint8)12U)

#define TMR_CTRL2_OC3NOIS_MASK           ((uint32)0x00002000U)
#define TMR_CTRL2_OC3NOIS_SHIFT          ((uint8)13U)

#define TMR_CTRL2_OC4OIS_MASK            ((uint32)0x00004000U)
#define TMR_CTRL2_OC4OIS_SHIFT           ((uint8)14U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_SMCTRL(Base + 0x08)
************************************************************************************************************/
/** TMRx_SMCTRL register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_SMCTRL_REG_ADDR(ModId)       ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x08U))

#define TMR_SMCTRL_SMFSEL_MASK           ((uint32)0x00000007U)
#define TMR_SMCTRL_SMFSEL_SHIFT          ((uint8)0U)

#define TMR_SMCTRL_OCCSEL_MASK           ((uint32)0x00000008U)
#define TMR_SMCTRL_OCCSEL_SHIFT          ((uint8)3U)

#define TMR_SMCTRL_TRGSEL_MASK           ((uint32)0x00000070U)
#define TMR_SMCTRL_TRGSEL_SHIFT          ((uint8)4U)

#define TMR_SMCTRL_MSMEN_MASK            ((uint32)0x00000080U)
#define TMR_SMCTRL_MSMEN_SHIFT           ((uint8)7U)

#define TMR_SMCTRL_ETFCFG_MASK           ((uint32)0x00000F00U)
#define TMR_SMCTRL_ETFCFG_SHIFT          ((uint8)8U)

#define TMR_SMCTRL_ETPCFG_MASK           ((uint32)0x00003000U)
#define TMR_SMCTRL_ETPCFG_SHIFT          ((uint8)12U)

#define TMR_SMCTRL_ECEN_MASK             ((uint32)0x00004000U)
#define TMR_SMCTRL_ECEN_SHIFT            ((uint8)14U)

#define TMR_SMCTRL_ETPOL_MASK            ((uint32)0x00008000U)
#define TMR_SMCTRL_ETPOL_SHIFT           ((uint8)15U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_DIEN(Base + 0x0C)
************************************************************************************************************/
/** TMRx_DIEN register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_DIEN_REG_ADDR(ModId)         ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x0CU))

#define TMR_DIEN_UIEN_MASK               ((uint32)0x00000001U)
#define TMR_DIEN_UIEN_SHIFT              ((uint8)0U)

#define TMR_DIEN_CC1IEN_MASK             ((uint32)0x00000002U)
#define TMR_DIEN_CC1IEN_SHIFT            ((uint8)1U)

#define TMR_DIEN_CC2IEN_MASK             ((uint32)0x00000004U)
#define TMR_DIEN_CC2IEN_SHIFT            ((uint8)2U)

#define TMR_DIEN_CC3IEN_MASK             ((uint32)0x00000008U)
#define TMR_DIEN_CC3IEN_SHIFT            ((uint8)3U)

#define TMR_DIEN_CC4IEN_MASK             ((uint32)0x00000010U)
#define TMR_DIEN_CC4IEN_SHIFT            ((uint8)4U)

#define TMR_DIEN_COMIEN_MASK             ((uint32)0x00000020U)
#define TMR_DIEN_COMIEN_SHIFT            ((uint8)5U)

#define TMR_DIEN_TRGIEN_MASK             ((uint32)0x00000040U)
#define TMR_DIEN_TRGIEN_SHIFT            ((uint8)6U)

#define TMR_DIEN_BRKIEN_MASK             ((uint32)0x00000080U)
#define TMR_DIEN_BRKIEN_SHIFT            ((uint8)7U)

#define TMR_DIEN_UDIEN_MASK              ((uint32)0x00000100U)
#define TMR_DIEN_UDIEN_SHIFT             ((uint8)8U)

#define TMR_DIEN_CC1DEN_MASK             ((uint32)0x00000200U)
#define TMR_DIEN_CC1DEN_SHIFT            ((uint8)9U)

#define TMR_DIEN_CC2DEN_MASK             ((uint32)0x00000400U)
#define TMR_DIEN_CC2DEN_SHIFT            ((uint8)10U)

#define TMR_DIEN_CC3DEN_MASK             ((uint32)0x00000800U)
#define TMR_DIEN_CC3DEN_SHIFT            ((uint8)11U)

#define TMR_DIEN_CC4DEN_MASK             ((uint32)0x00001000U)
#define TMR_DIEN_CC4DEN_SHIFT            ((uint8)12U)

#define TMR_DIEN_COMDEN_MASK             ((uint32)0x00002000U)
#define TMR_DIEN_COMDEN_SHIFT            ((uint8)13U)

#define TMR_DIEN_TRGDEN_MASK             ((uint32)0x00004000U)
#define TMR_DIEN_TRGDEN_SHIFT            ((uint8)14U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_STS(Base + 0x10)
************************************************************************************************************/
/** TMRx_STS register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_STS_REG_ADDR(ModId)          ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x10U))

#define TMR_STS_UIFLG_MASK               ((uint32)0x00000001U)
#define TMR_STS_UIFLG_SHIFT              ((uint8)0U)

#define TMR_STS_CC1IFLG_MASK             ((uint32)0x00000002U)
#define TMR_STS_CC1IFLG_SHIFT            ((uint8)1U)

#define TMR_STS_CC2IFLG_MASK             ((uint32)0x00000004U)
#define TMR_STS_CC2IFLG_SHIFT            ((uint8)2U)

#define TMR_STS_CC3IFLG_MASK             ((uint32)0x00000008U)
#define TMR_STS_CC3IFLG_SHIFT            ((uint8)3U)

#define TMR_STS_CC4IFLG_MASK             ((uint32)0x00000010U)
#define TMR_STS_CC4IFLG_SHIFT            ((uint8)4U)

#define TMR_STS_COMIFLG_MASK             ((uint32)0x00000020U)
#define TMR_STS_COMIFLG_SHIFT            ((uint8)5U)

#define TMR_STS_TRGIFLG_MASK             ((uint32)0x00000040U)
#define TMR_STS_TRGIFLG_SHIFT            ((uint8)6U)

#define TMR_STS_BRKIFLG_MASK             ((uint32)0x00000080U)
#define TMR_STS_BRKIFLG_SHIFT            ((uint8)7U)

#define TMR_STS_CC1RCFLG_MASK            ((uint32)0x00000200U)
#define TMR_STS_CC1RCFLG_SHIFT           ((uint8)9U)

#define TMR_STS_CC2RCFLG_MASK            ((uint32)0x00000400U)
#define TMR_STS_CC2RCFLG_SHIFT           ((uint8)10U)

#define TMR_STS_CC3RCFLG_MASK            ((uint32)0x00000800U)
#define TMR_STS_CC3RCFLG_SHIFT           ((uint8)11U)

#define TMR_STS_CC4RCFLG_MASK            ((uint32)0x00001000U)
#define TMR_STS_CC4RCFLG_SHIFT           ((uint8)12U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CEG(Base + 0x14)
************************************************************************************************************/
/** TMRx_CEG register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CEG_REG_ADDR(ModId)          ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x14U))

#define TMR_CEG_UEG_MASK                 ((uint32)0x00000001U)
#define TMR_CEG_UEG_SHIFT                ((uint8)0U)

#define TMR_CEG_CC1EG_MASK               ((uint32)0x00000002U)
#define TMR_CEG_CC1EG_SHIFT              ((uint8)1U)

#define TMR_CEG_CC2EG_MASK               ((uint32)0x00000004U)
#define TMR_CEG_CC2EG_SHIFT              ((uint8)2U)

#define TMR_CEG_CC3EG_MASK               ((uint32)0x00000008U)
#define TMR_CEG_CC3EG_SHIFT              ((uint8)3U)

#define TMR_CEG_CC4EG_MASK               ((uint32)0x00000010U)
#define TMR_CEG_CC4EG_SHIFT              ((uint8)4U)

#define TMR_CEG_COMG_MASK                ((uint32)0x00000020U)
#define TMR_CEG_COMG_SHIFT               ((uint8)5U)

#define TMR_CEG_TEG_MASK                 ((uint32)0x00000040U)
#define TMR_CEG_TEG_SHIFT                ((uint8)6U)

#define TMR_CEG_BEG_MASK                 ((uint32)0x00000080U)
#define TMR_CEG_BEG_SHIFT                ((uint8)7U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CCM1(Base + 0x18)
************************************************************************************************************/
/** TMRx_CCM1 register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CCM1_REG_ADDR(ModId)         ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x18U))

/** Output Comparison Mode */
#define TMR_CCM1_CC1SEL_MASK             ((uint32)0x00000003U)
#define TMR_CCM1_CC1SEL_SHIFT            ((uint8)0U)

#define TMR_CCM1_OC1FEN_MASK             ((uint32)0x00000004U)
#define TMR_CCM1_OC1FEN_SHIFT            ((uint8)2U)

#define TMR_CCM1_OC1PEN_MASK             ((uint32)0x00000008U)
#define TMR_CCM1_OC1PEN_SHIFT            ((uint8)3U)

#define TMR_CCM1_OC1MOD_MASK             ((uint32)0x00000070U)
#define TMR_CCM1_OC1MOD_SHIFT            ((uint8)4U)

#define TMR_CCM1_OC1CEN_MASK             ((uint32)0x00000080U)
#define TMR_CCM1_OC1CEN_SHIFT            ((uint8)7U)

#define TMR_CCM1_CC2SEL_MASK             ((uint32)0x00000300U)
#define TMR_CCM1_CC2SEL_SHIFT            ((uint8)8U)

#define TMR_CCM1_OC2FEN_MASK             ((uint32)0x00000400U)
#define TMR_CCM1_OC2FEN_SHIFT            ((uint8)10U)

#define TMR_CCM1_OC2PEN_MASK             ((uint32)0x00000800U)
#define TMR_CCM1_OC2PEN_SHIFT            ((uint8)11U)

#define TMR_CCM1_OC2MOD_MASK             ((uint32)0x00007000U)
#define TMR_CCM1_OC2MOD_SHIFT            ((uint8)12U)

#define TMR_CCM1_OC2CEN_MASK             ((uint32)0x00008000U)
#define TMR_CCM1_OC2CEN_SHIFT            ((uint8)15U)

/** Input Capture Mode */
#define TMR_CCM1_IC1PSC_MASK             ((uint32)0x0000000CU)
#define TMR_CCM1_IC1PSC_SHIFT            ((uint8)2U)

#define TMR_CCM1_IC1F_MASK               ((uint32)0x000000F0U)
#define TMR_CCM1_IC1F_SHIFT              ((uint8)4U)

#define TMR_CCM1_IC2PSC_MASK             ((uint32)0x00000C00U)
#define TMR_CCM1_IC2PSC_SHIFT            ((uint8)10U)

#define TMR_CCM1_IC2F_MASK               ((uint32)0x0000F000U)
#define TMR_CCM1_IC2F_SHIFT              ((uint8)12U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CCM2(Base + 0x1C)
************************************************************************************************************/
/** TMRx_CCM2 register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CCM2_REG_ADDR(ModId)         ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x1CU))

/** Output Comparison Mode */
#define TMR_CCM2_CC3SEL_MASK             ((uint32)0x00000003U)
#define TMR_CCM2_CC3SEL_SHIFT            ((uint8)0U)

#define TMR_CCM2_OC3FEN_MASK             ((uint32)0x00000004U)
#define TMR_CCM2_OC3FEN_SHIFT            ((uint8)2U)

#define TMR_CCM2_OC3PEN_MASK             ((uint32)0x00000008U)
#define TMR_CCM2_OC3PEN_SHIFT            ((uint8)3U)

#define TMR_CCM2_OC3MOD_MASK             ((uint32)0x00000070U)
#define TMR_CCM2_OC3MOD_SHIFT            ((uint8)4U)

#define TMR_CCM2_OC3CEN_MASK             ((uint32)0x00000080U)
#define TMR_CCM2_OC3CEN_SHIFT            ((uint8)7U)

#define TMR_CCM2_CC4SEL_MASK             ((uint32)0x00000300U)
#define TMR_CCM2_CC4SEL_SHIFT            ((uint8)8U)

#define TMR_CCM2_OC4FEN_MASK             ((uint32)0x00000400U)
#define TMR_CCM2_OC4FEN_SHIFT            ((uint8)10U)

#define TMR_CCM2_OC4PEN_MASK             ((uint32)0x00000800U)
#define TMR_CCM2_OC4PEN_SHIFT            ((uint8)11U)

#define TMR_CCM2_OC4MOD_MASK             ((uint32)0x00007000U)
#define TMR_CCM2_OC4MOD_SHIFT            ((uint8)12U)

#define TMR_CCM2_OC4CEN_MASK             ((uint32)0x00008000U)
#define TMR_CCM2_OC4CEN_SHIFT            ((uint8)15U)

/** Input Capture Mode */
#define TMR_CCM2_IC3PSC_MASK             ((uint32)0x0000000CU)
#define TMR_CCM2_IC3PSC_SHIFT            ((uint8)2U)

#define TMR_CCM2_IC3F_MASK               ((uint32)0x000000F0U)
#define TMR_CCM2_IC3F_SHIFT              ((uint8)4U)

#define TMR_CCM2_IC4PSC_MASK             ((uint32)0x00000C00U)
#define TMR_CCM2_IC4PSC_SHIFT            ((uint8)10U)

#define TMR_CCM2_IC4F_MASK               ((uint32)0x0000F000U)
#define TMR_CCM2_IC4F_SHIFT              ((uint8)12U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CCEN(Base + 0x20)
************************************************************************************************************/
/** TMRx_CCEN register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CCEN_REG_ADDR(ModId)         ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x20U))

#define TMR_CCEN_CC1EN_MASK              ((uint32)0x00000001U)
#define TMR_CCEN_CC1EN_SHIFT             ((uint8)0U)

#define TMR_CCEN_CC1POL_MASK             ((uint32)0x00000002U)
#define TMR_CCEN_CC1POL_SHIFT            ((uint8)1U)

#define TMR_CCEN_CC1NEN_MASK             ((uint32)0x00000004U)
#define TMR_CCEN_CC1NEN_SHIFT            ((uint8)2U)

#define TMR_CCEN_CC1NPOL_MASK            ((uint32)0x00000008U)
#define TMR_CCEN_CC1NPOL_SHIFT           ((uint8)3U)

#define TMR_CCEN_CC2EN_MASK              ((uint32)0x00000010U)
#define TMR_CCEN_CC2EN_SHIFT             ((uint8)4U)

#define TMR_CCEN_CC2POL_MASK             ((uint32)0x00000020U)
#define TMR_CCEN_CC2POL_SHIFT            ((uint8)5U)

#define TMR_CCEN_CC2NEN_MASK             ((uint32)0x00000040U)
#define TMR_CCEN_CC2NEN_SHIFT            ((uint8)6U)

#define TMR_CCEN_CC2NPOL_MASK            ((uint32)0x00000080U)
#define TMR_CCEN_CC2NPOL_SHIFT           ((uint8)7U)

#define TMR_CCEN_CC3EN_MASK              ((uint32)0x00000100U)
#define TMR_CCEN_CC3EN_SHIFT             ((uint8)8U)

#define TMR_CCEN_CC3POL_MASK             ((uint32)0x00000200U)
#define TMR_CCEN_CC3POL_SHIFT            ((uint8)9U)

#define TMR_CCEN_CC3NEN_MASK             ((uint32)0x00000400U)
#define TMR_CCEN_CC3NEN_SHIFT            ((uint8)10U)

#define TMR_CCEN_CC3NPOL_MASK            ((uint32)0x00000800U)
#define TMR_CCEN_CC3NPOL_SHIFT           ((uint8)11U)

#define TMR_CCEN_CC4EN_MASK              ((uint32)0x00001000U)
#define TMR_CCEN_CC4EN_SHIFT             ((uint8)12U)

#define TMR_CCEN_CC4POL_MASK             ((uint32)0x00002000U)
#define TMR_CCEN_CC4POL_SHIFT            ((uint8)13U)

#define TMR_CCEN_CC4NPOL_MASK            ((uint32)0x00008000U)
#define TMR_CCEN_CC4NPOL_SHIFT           ((uint8)15U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CNT(Base + 0x24)
************************************************************************************************************/
/** TMRx_CNT register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CNT_REG_ADDR(ModId)          ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x24U))

#define TMR_CNT_MASK                     ((uint32)0x0000FFFFU)
#define TMR_CNT_SHIFT                    ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_PSC(Base + 0x28)
************************************************************************************************************/
/** TMRx_PSC register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_PSC_REG_ADDR(ModId)          ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x28U))

#define TMR_PSC_MASK                     ((uint32)0x0000FFFFU)
#define TMR_PSC_SHIFT                    ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_AUTORLD(Base + 0x2C)
************************************************************************************************************/
/** TMRx_AUTORLD register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_AUTORLD_REG_ADDR(ModId)      ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x2CU))

#define TMR_AUTORLD_MASK                 ((uint32)0x0000FFFFU)
#define TMR_AUTORLD_SHIFT                ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_REPCNT(Base + 0x30)
************************************************************************************************************/
/** TMRx_REPCNT register address */
/** Note: The value of ModId can be 1. */
#define TMR_REPCNT_REG_ADDR(ModId)       ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x30U))

#define TMR_REPCNT_MASK                  ((uint32)0x000000FFU)
#define TMR_REPCNT_SHIFT                 ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CC1(Base + 0x34)
************************************************************************************************************/
/** TMRx_CC1 register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CC1_REG_ADDR(ModId)          ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x34U))

#define TMR_CC1_MASK                     ((uint32)0x0000FFFFU)
#define TMR_CC1_SHIFT                    ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CC2(Base + 0x38)
************************************************************************************************************/
/** TMRx_CC2 register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CC2_REG_ADDR(ModId)          ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x38U))

#define TMR_CC2_MASK                     ((uint32)0x0000FFFFU)
#define TMR_CC2_SHIFT                    ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CC3(Base + 0x3C)
************************************************************************************************************/
/** TMRx_CC3 register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CC3_REG_ADDR(ModId)          ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x3CU))

#define TMR_CC3_MASK                     ((uint32)0x0000FFFFU)
#define TMR_CC3_SHIFT                    ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_CC4(Base + 0x40)
************************************************************************************************************/
/** TMRx_CC4 register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_CC4_REG_ADDR(ModId)          ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x40U))

#define TMR_CC4_MASK                     ((uint32)0x0000FFFFU)
#define TMR_CC4_SHIFT                    ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_BDT(Base + 0x44)
************************************************************************************************************/
/** TMRx_BDT register address */
/** Note: The value of ModId can be 1. */
#define TMR_BDT_REG_ADDR(ModId)          ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x44U))

#define TMR_BDT_DTS_MASK                 ((uint32)0x000000FFU)
#define TMR_BDT_DTS_SHIFT                ((uint8)0U)

#define TMR_BDT_LOCKCFG_MASK             ((uint32)0x00000300U)
#define TMR_BDT_LOCKCFG_SHIFT            ((uint8)8U)

#define TMR_BDT_IMOS_MASK                ((uint32)0x00000400U)
#define TMR_BDT_IMOS_SHIFT               ((uint8)10U)

#define TMR_BDT_RMOS_MASK                ((uint32)0x00000800U)
#define TMR_BDT_RMOS_SHIFT               ((uint8)11U)

#define TMR_BDT_BRKEN_MASK               ((uint32)0x00001000U)
#define TMR_BDT_BRKEN_SHIFT              ((uint8)12U)

#define TMR_BDT_BRKPOL_MASK              ((uint32)0x00002000U)
#define TMR_BDT_BRKPOL_SHIFT             ((uint8)13U)

#define TMR_BDT_AOEN_MASK                ((uint32)0x00004000U)
#define TMR_BDT_AOEN_SHIFT               ((uint8)14U)

#define TMR_BDT_MOEN_MASK                ((uint32)0x00008000U)
#define TMR_BDT_MOEN_SHIFT               ((uint8)15U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_DCTRL(Base + 0x48)
************************************************************************************************************/
/** TMRx_DCTRL register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_DCTRL_REG_ADDR(ModId)        ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x48U))

#define TMR_DCTRL_DBADDR_MASK            ((uint32)0x0000001FU)
#define TMR_DCTRL_DBADDR_SHIFT           ((uint8)0U)

#define TMR_DCTRL_DBLEN_MASK             ((uint32)0x00001F00U)
#define TMR_DCTRL_DBLEN_SHIFT            ((uint8)8U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMRx_DMADDR(Base + 0x4C)
************************************************************************************************************/
/** TMRx_DMADDR register address */
/** Note: The value of ModId can be 1, 2, 3, 4. */
#define TMR_DMADDR_REG_ADDR(ModId)       ((uint32)(TMR_BASEADDR_ARR[ModId] + (uint32)0x4CU))

#define TMR_DMADDR_DMADDR_MASK           ((uint32)0x0000FFFFU)
#define TMR_DMADDR_DMADDR_SHIFT          ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: TMR3_OPT(Base + 0x50)
************************************************************************************************************/
/** TMR3_OPT register address */
#define TMR3_OPT_REG_ADDR                ((uint32)(TMR_BASEADDR_ARR[2] + (uint32)0x50U))

#define TMR3_OPT_RMPSEL_MASK             ((uint32)0x0000FFFFU)
#define TMR3_OPT_RMPSEL_SHIFT            ((uint8)0U)

/**@} end of group PDL_Macros */
/***********************************************************************************************************
                                             GLOBAL VARIABLE
************************************************************************************************************/
/** @defgroup PDL_Variable
  @{
*/
/** The declaration of the timer base address array */
extern CONST(uint32, GPT_CONST) TMR_BASEADDR_ARR[9];

/**@} end of group PDL_Variable */
#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* PDL_TMR_REG_H */
/**@} end of group PDL_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
