/*!
* @file     Crypto_ShaReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the SHA256 module.
 *          This header file includes the register definitions of the SHA256 module.
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_15-Nov-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef CRYPTO_SHA_REG_H
#define CRYPTO_SHA_REG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"
/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup CRYPTO_Driver
  * @brief CRYPTO driver modules
  @{
*/

/** @defgroup CRYPTO_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define CRYPTO_SHA_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define CRYPTO_SHA_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define CRYPTO_SHA_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define CRYPTO_SHA_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define CRYPTO_SHA_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define CRYPTO_SHA_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define CRYPTO_SHA_REG_H_SW_PATCH_VERSION                        0x00U

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Crypto_ShaReg.h and Reg_eSys.h */
    #if (CRYPTO_SHA_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Crypto_ShaReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Crypto_ShaReg.h and Reg_eSys.h */
    #if (CRYPTO_SHA_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Crypto_ShaReg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
                                            MACRO DEFINITION
************************************************************************************************************/


/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: VERID (Base + 0x00)
************************************************************************************************************/
/** VERID register address */
#define SHA256_VERID_REG_ADDR               ((uint32)(SHA256_BASEADDR + (uint32)0U))

#define SHA256_VERID_MIN_MASK               ((uint32)0x000000FFU)
#define SHA256_VERID_MIN_SHIFT              ((uint8)0U)

#define SHA256_VERID_MID_MASK               ((uint32)0x0000FF00U)
#define SHA256_VERID_MID_SHIFT              ((uint8)8U)

#define SHA256_VERID_MAJ_MASK               ((uint32)0x00FF0000U)
#define SHA256_VERID_MAJ_SHIFT              ((uint8)16U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: CTRL (Base + 0x04)
************************************************************************************************************/
/** CTRL register address */
#define SHA256_CTRL_REG_ADDR                ((uint32)(SHA256_BASEADDR + (uint32)0x04U))

#define SHA256_CTRL_OP_START_MASK           ((uint32)0x00000001U)
#define SHA256_CTRL_OP_START_SHIFT          ((uint8)0U)

#define SHA256_CTRL_IE_MASK                 ((uint32)0x00000002U)
#define SHA256_CTRL_IE_SHIFT                ((uint8)1U)

#define SHA256_CTRL_TYPE_MASK               ((uint32)0x0000003CU)
#define SHA256_CTRL_TYPE_SHIFT              ((uint8)2U)

#define SHA256_CTRL_INI_MODE_MASK           ((uint32)0x00000040U)
#define SHA256_CTRL_INI_MODE_SHIFT          ((uint8)6U)

#define SHA256_CTRL_PAD_MODE_MASK           ((uint32)0x00000080U)
#define SHA256_CTRL_PAD_MODE_SHIFT          ((uint8)7U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: STATUS (Base + 0x08)
************************************************************************************************************/
/** STATUS register address */
#define SHA256_STATUS_REG_ADDR              ((uint32)(SHA256_BASEADDR + (uint32)0x08U))

#define SHA256_STATUS_OP_DONE_MASK          ((uint32)0x00000001U)
#define SHA256_STATUS_OP_DONE_SHIFT         ((uint8)0U)

#define SHA256_STATUS_BUSY_MASK             ((uint32)0x00000002U)
#define SHA256_STATUS_BUSY_SHIFT            ((uint8)1U)

#define SHA256_STATUS_INTR_MASK             ((uint32)0x00000004U)
#define SHA256_STATUS_INTR_SHIFT            ((uint8)2U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: BLKN (Base + 0x0C)
************************************************************************************************************/
/** BLKN register address */
#define SHA256_BLKN_REG_ADDR                ((uint32)(SHA256_BASEADDR + (uint32)0x0CU))

#define SHA256_BLKN_MASK                    ((uint32)0x0000003FU)
#define SHA256_BLKN_SHIFT                   ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DILH (Base + 0x10)
************************************************************************************************************/
/** DILH register address */
#define SHA256_DILH_REG_ADDR                ((uint32)(SHA256_BASEADDR + (uint32)0x10U))

#define SHA256_DILH_MASK                    ((uint32)0xFFFFFFFFU)
#define SHA256_DILH_SHIFT                   ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DILL (Base + 0x14)
************************************************************************************************************/
/** DILL register address */
#define SHA256_DILL_REG_ADDR                ((uint32)(SHA256_BASEADDR + (uint32)0x14U))

#define SHA256_DILL_MASK                    ((uint32)0xFFFFFFFFU)
#define SHA256_DILH_SHIFT                   ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DIN (Base + 0x18)
************************************************************************************************************/
/** DIN register address */
#define SHA256_DIN_REG_ADDR                 ((uint32)(SHA256_BASEADDR + (uint32)0x18U))

#define SHA256_DIN_MASK                     ((uint32)0xFFFFFFFFU)
#define SHA256_DIN_SHIFT                    ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DOUT (Base + 0x1C~0x58)
************************************************************************************************************/
/** DOUT register address */
/** Note: The value of RegIndex can be 0 ~ 15. */
#define SHA256_DOUT_REG_ADDR(RegIndex)      ((uint32)(SHA256_BASEADDR + 0x1CU + ((uint32)4u * (uint32)RegIndex)))

#define SHA256_DOUT_MASK                    ((uint32)0xFFFFFFFFU)
#define SHA256_DOUT_SHIFT                   ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DIGEST (Base + 0x5C)
************************************************************************************************************/
/** DIGEST register address */
#define SHA256_DIGEST_REG_ADDR              ((uint32)(SHA256_BASEADDR + (uint32)0x5CU))

#define SHA256_DIGEST_IV_MASK               ((uint32)0xFFFFFFFFU)
#define SHA256_DIGEST_IV_SHIFT              ((uint8)0U)

/**@} end of group CRYPTO_Macros */
#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* CRYPTO_SHA_REG_H */
/**@} end of group CRYPTO_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
