/*!
* @file     Mcu_RcmReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the reset and clock management(RCM) module.
*
* @details  This header file includes the register definitions of the reset and clock management(RCM) module.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/


#ifndef MCU_RCMREG_H
#define MCU_RCMREG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @addtogroup MCU_Driver
  @{
*/

/** @defgroup MCU_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
***********************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define MCU_RCM_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define MCU_RCM_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_RCM_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_RCM_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_RCM_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_RCM_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_RCM_REG_H_SW_PATCH_VERSION                        0x00U

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
***********************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Mcu_RcmReg.h and Reg_eSys.h */
    #if (MCU_RCM_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Mcu_RcmReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Mcu_RcmReg.h and Reg_eSys.h */
    #if (MCU_RCM_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Mcu_RcmReg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_CTRL1 (Base + 0x00)
************************************************************************************************************/
/** RCM_CTRL1 register address */
#define RCM_CTRL1_REG_ADDR               ((uint32)(RCM_BASEADDR + (uint32)0x00U))

#define RCM_CTRL1_HSIEN_MASK             ((uint32)0x00000001U)
#define RCM_CTRL1_HSIEN_SHIFT            ((uint8)0U)

#define RCM_CTRL1_HSIRDYFLG_MASK         ((uint32)0x00000002U)
#define RCM_CTRL1_HSIRDYFLG_SHIFT        ((uint8)1U)

#define RCM_CTRL1_HSITRM_MASK            ((uint32)0x000000F8U)
#define RCM_CTRL1_HSITRM_SHIFT           ((uint8)3U)

#define RCM_CTRL1_HSICAL_MASK            ((uint32)0x0000FF00U)
#define RCM_CTRL1_HSICAL_SHIFT           ((uint8)8U)

#define RCM_CTRL1_HSEEN_MASK             ((uint32)0x00010000U)
#define RCM_CTRL1_HSEEN_SHIFT            ((uint8)16U)

#define RCM_CTRL1_HSERDYFLG_MASK         ((uint32)0x00020000U)
#define RCM_CTRL1_HSERDYFLG_SHIFT        ((uint8)17U)

#define RCM_CTRL1_HSEBCFG_MASK           ((uint32)0x00040000U)
#define RCM_CTRL1_HSEBCFG_SHIFT          ((uint8)18U)

#define RCM_CTRL1_CSSEN_MASK             ((uint32)0x00080000U)
#define RCM_CTRL1_CSSEN_SHIFT            ((uint8)19U)

#define RCM_CTRL1_PLLEN_MASK             ((uint32)0x01000000U)
#define RCM_CTRL1_PLLEN_SHIFT            ((uint8)24U)

#define RCM_CTRL1_PLLRDYFLG_MASK         ((uint32)0x02000000U)
#define RCM_CTRL1_PLLRDYFLG_SHIFT        ((uint8)25U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_CFG1 (Base + 0x04)
************************************************************************************************************/
/** RCM_CFG1 register address */
#define RCM_CFG1_REG_ADDR                ((uint32)(RCM_BASEADDR + (uint32)0x04U))

#define RCM_CFG1_SCLKSEL_MASK            ((uint32)0x00000003U)
#define RCM_CFG1_SCLKSEL_SHIFT           ((uint8)0U)

#define RCM_CFG1_SCLKSELSTS_MASK         ((uint32)0x0000000CU)
#define RCM_CFG1_SCLKSELSTS_SHIFT        ((uint8)2U)

#define RCM_CFG1_AHBPSC_MASK             ((uint32)0x000000F0U)
#define RCM_CFG1_AHBPSC_SHIFT            ((uint8)4U)

#define RCM_CFG1_APB1PSC_MASK            ((uint32)0x00000700U)
#define RCM_CFG1_APB1PSC_SHIFT           ((uint8)8U)

#define RCM_CFG1_PLLSRCSEL_MASK          ((uint32)0x00010000U)
#define RCM_CFG1_PLLSRCSEL_SHIFT         ((uint8)16U)

#define RCM_CFG1_PLLHSEPSC_MASK          ((uint32)0x00020000U)
#define RCM_CFG1_PLLHSEPSC_SHIFT         ((uint8)17U)

#define RCM_CFG1_PLLMULCFG_MASK          ((uint32)0x003C0000U)
#define RCM_CFG1_PLLMULCFG_SHIFT         ((uint8)18U)

#define RCM_CFG1_MCOSEL_MASK             ((uint32)0x0F000000U)
#define RCM_CFG1_MCOSEL_SHIFT            ((uint8)24U)

#define RCM_CFG1_MCOPRE_MASK             ((uint32)0x70000000U)
#define RCM_CFG1_MCOPRE_SHIFT            ((uint8)28U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_INT1 (Base + 0x08)
************************************************************************************************************/
/** RCM_INT register address */
#define RCM_INT1_REG_ADDR                 ((uint32)(RCM_BASEADDR + (uint32)0x08U))

#define RCM_INT1_LSIRDYFLG_MASK           ((uint32)0x00000001U)
#define RCM_INT1_LSIRDYFLG_SHIFT          ((uint8)0U)

#define RCM_INT1_HSIRDYFLG_MASK           ((uint32)0x00000004U)
#define RCM_INT1_HSIRDYFLG_SHIFT          ((uint8)2U)

#define RCM_INT1_HSERDYFLG_MASK           ((uint32)0x00000008U)
#define RCM_INT1_HSERDYFLG_SHIFT          ((uint8)3U)

#define RCM_INT1_PLLRDYFLG_MASK           ((uint32)0x00000010U)
#define RCM_INT1_PLLRDYFLG_SHIFT          ((uint8)4U)

#define RCM_INT1_HSI14RDYFLG_MASK         ((uint32)0x00000020U)
#define RCM_INT1_HSI14RDYFLG_SHIFT        ((uint8)5U)

#define RCM_INT1_CSSFLG_MASK              ((uint32)0x00000080U)
#define RCM_INT1_CSSFLG_SHIFT             ((uint8)7U)

#define RCM_INT1_LSIRDYEN_MASK            ((uint32)0x00000100U)
#define RCM_INT1_LSIRDYEN_SHIFT           ((uint8)8U)

#define RCM_INT1_HSIRDYEN_MASK            ((uint32)0x00000400U)
#define RCM_INT1_HSIRDYEN_SHIFT           ((uint8)10U)

#define RCM_INT1_HSERDYEN_MASK            ((uint32)0x00000800U)
#define RCM_INT1_HSERDYEN_SHIFT           ((uint8)11U)

#define RCM_INT1_PLLRDYEN_MASK            ((uint32)0x00001000U)
#define RCM_INT1_PLLRDYEN_SHIFT           ((uint8)12U)

#define RCM_INT1_HSI14RDYEN_MASK          ((uint32)0x00002000U)
#define RCM_INT1_HSI14RDYEN_SHIFT         ((uint8)13U)

#define RCM_INT1_LSIRDYCLR_MASK           ((uint32)0x00010000U)
#define RCM_INT1_LSIRDYCLR_SHIFT          ((uint8)16U)

#define RCM_INT1_HSIRDYCLR_MASK           ((uint32)0x00040000U)
#define RCM_INT1_HSIRDYCLR_SHIFT          ((uint8)18U)

#define RCM_INT1_HSERDYCLR_MASK           ((uint32)0x00080000U)
#define RCM_INT1_HSERDYCLR_SHIFT          ((uint8)19U)

#define RCM_INT1_PLLRDYCLR_MASK           ((uint32)0x00100000U)
#define RCM_INT1_PLLRDYCLR_SHIFT          ((uint8)20U)

#define RCM_INT1_HSI14RDYCLR_MASK         ((uint32)0x00200000U)
#define RCM_INT1_HSI14RDYCLR_SHIFT        ((uint8)21U)

#define RCM_INT1_CSSCLR_MASK              ((uint32)0x00800000U)
#define RCM_INT1_CSSCLR_SHIFT             ((uint8)23U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_APBRST2 (Base + 0x0C)
************************************************************************************************************/
/** RCM_APBRST2 register address */
#define RCM_APBRST2_REG_ADDR             ((uint32)(RCM_BASEADDR + (uint32)0x0CU))

#define RCM_APBRST2_SYSCFGRST_MASK       ((uint32)0x00000001U)
#define RCM_APBRST2_SYSCFGRST_SHIFT      ((uint8)0U)

#define RCM_APBRST2_ADCRST_MASK          ((uint32)0x00000200U)
#define RCM_APBRST2_ADCRST_SHIFT         ((uint8)9U)

#define RCM_APBRST2_TMR1RST_MASK         ((uint32)0x00000800U)
#define RCM_APBRST2_TMR1RST_SHIFT        ((uint8)11U)

#define RCM_APBRST2_SPI1RST_MASK         ((uint32)0x00001000U)
#define RCM_APBRST2_SPI1RST_SHIFT        ((uint8)12U)

#define RCM_APBRST2_USART1RST_MASK       ((uint32)0x00004000U)
#define RCM_APBRST2_USART1RST_SHIFT      ((uint8)14U)

#define RCM_APBRST2_TMR8RST_MASK         ((uint32)0x00008000U)
#define RCM_APBRST2_TMR8RST_SHIFT        ((uint8)15U)

#define RCM_APBRST2_DBGRST_MASK          ((uint32)0x00400000U)
#define RCM_APBRST2_DBGRST_SHIFT         ((uint8)22U)

#define RCM_APBRST2_SMSRST_MASK          ((uint32)0x00800000U)
#define RCM_APBRST2_SMSRST_SHIFT         ((uint8)23U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_APBRST1 (Base + 0x10)
************************************************************************************************************/
/** RCM_APBRST1 register address */
#define RCM_APBRST1_REG_ADDR             ((uint32)(RCM_BASEADDR + (uint32)0x10U))

#define RCM_APBRST1_TMR2RST_MASK         ((uint32)0x00000001U)
#define RCM_APBRST1_TMR2RST_SHIFT        ((uint8)0U)

#define RCM_APBRST1_TMR3RST_MASK         ((uint32)0x00000002U)
#define RCM_APBRST1_TMR3RST_SHIFT        ((uint8)1U)

#define RCM_APBRST1_TMR4RST_MASK         ((uint32)0x00000004U)
#define RCM_APBRST1_TMR4RST_SHIFT        ((uint8)2U)

#define RCM_APBRST1_TMR6RST_MASK         ((uint32)0x00000010U)
#define RCM_APBRST1_TMR6RST_SHIFT        ((uint8)4U)

#define RCM_APBRST1_TMR7RST_MASK         ((uint32)0x00000020U)
#define RCM_APBRST1_TMR7RST_SHIFT        ((uint8)5U)

#define RCM_APBRST1_WWDTRST_MASK         ((uint32)0x00000800U)
#define RCM_APBRST1_WWDTRST_SHIFT        ((uint8)11U)

#define RCM_APBRST1_USART2RST_MASK       ((uint32)0x00020000U)
#define RCM_APBRST1_USART2RST_SHIFT      ((uint8)17U)

#define RCM_APBRST1_CANRST_MASK          ((uint32)0x02000000U)
#define RCM_APBRST1_CANRST_SHIFT         ((uint8)25U)

#define RCM_APBRST1_PMURST_MASK          ((uint32)0x10000000U)
#define RCM_APBRST1_PMURST_SHIFT         ((uint8)28U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_AHBCLKEN (Base + 0x14)
************************************************************************************************************/
/** RCM_AHBCLKEN register address */
#define RCM_AHBCLKEN_REG_ADDR            ((uint32)(RCM_BASEADDR + (uint32)0x14U))

#define RCM_AHBCLKEN_DMA1EN_MASK         ((uint32)0x00000001U)
#define RCM_AHBCLKEN_DMA1EN_SHIFT        ((uint8)0U)

#define RCM_AHBCLKEN_SRAMEN_MASK         ((uint32)0x00000004U)
#define RCM_AHBCLKEN_SRAMEN_SHIFT        ((uint8)2U)

#define RCM_AHBCLKEN_FMCEN_MASK          ((uint32)0x00000010U)
#define RCM_AHBCLKEN_FMCEN_SHIFT         ((uint8)4U)

#define RCM_AHBCLKEN_CRCEN_MASK          ((uint32)0x00000040U)
#define RCM_AHBCLKEN_CRCEN_SHIFT         ((uint8)6U)

#define RCM_AHBCLKEN_TRNGEN_MASK         ((uint32)0x00000080U)
#define RCM_AHBCLKEN_TRNGEN_SHIFT        ((uint8)7U)

#define RCM_AHBCLKEN_SHAEN_MASK          ((uint32)0x00000100U)
#define RCM_AHBCLKEN_SHAEN_SHIFT         ((uint8)8U)

#define RCM_AHBCLKEN_AES256EN_MASK       ((uint32)0x00000200U)
#define RCM_AHBCLKEN_AES256EN_SHIFT      ((uint8)9U)

#define RCM_AHBCLKEN_PAEN_MASK           ((uint32)0x00020000U)
#define RCM_AHBCLKEN_PAEN_SHIFT          ((uint8)17U)

#define RCM_AHBCLKEN_PBEN_MASK           ((uint32)0x00040000U)
#define RCM_AHBCLKEN_PBEN_SHIFT          ((uint8)18U)

#define RCM_AHBCLKEN_PCEN_MASK           ((uint32)0x00080000U)
#define RCM_AHBCLKEN_PCEN_SHIFT          ((uint8)19U)

#define RCM_AHBCLKEN_PDEN_MASK           ((uint32)0x00100000U)
#define RCM_AHBCLKEN_PDEN_SHIFT          ((uint8)20U)

#define RCM_AHBCLKEN_PFEN_MASK           ((uint32)0x00400000U)
#define RCM_AHBCLKEN_PFEN_SHIFT          ((uint8)22U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_APBCLKEN2 (Base + 0x18)
************************************************************************************************************/
/** RCM_APBCLKEN2 register address */
#define RCM_APBCLKEN2_REG_ADDR           ((uint32)(RCM_BASEADDR + (uint32)0x18U))

#define RCM_APBCLKEN2_SCFGEN_MASK        ((uint32)0x00000001U)
#define RCM_APBCLKEN2_SCFGEN_SHIFT       ((uint8)0U)

#define RCM_APBCLKEN2_ADCEN_MASK         ((uint32)0x00000200U)
#define RCM_APBCLKEN2_ADCEN_SHIFT        ((uint8)9U)

#define RCM_APBCLKEN2_TMR1EN_MASK        ((uint32)0x00000800U)
#define RCM_APBCLKEN2_TMR1EN_SHIFT       ((uint8)11U)

#define RCM_APBCLKEN2_SPIEN_MASK         ((uint32)0x00001000U)
#define RCM_APBCLKEN2_SPIEN_SHIFT        ((uint8)12U)

#define RCM_APBCLKEN2_USART1EN_MASK      ((uint32)0x00004000U)
#define RCM_APBCLKEN2_USART1EN_SHIFT     ((uint8)14U)

#define RCM_APBCLKEN2_TMR8EN_MASK        ((uint32)0x00008000U)
#define RCM_APBCLKEN2_TMR8EN_SHIFT       ((uint8)15U)

#define RCM_APBCLKEN2_DBGEN_MASK         ((uint32)0x00400000U)
#define RCM_APBCLKEN2_DBGEN_SHIFT        ((uint8)22U)

#define RCM_APBCLKEN2_SMSEN_MASK         ((uint32)0x00800000U)
#define RCM_APBCLKEN2_SMSEN_SHIFT        ((uint8)23U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_APBCLKEN1 (Base + 0x1C)
************************************************************************************************************/
/** RCM_APBCLKEN1 register address */
#define RCM_APBCLKEN1_REG_ADDR           ((uint32)(RCM_BASEADDR + (uint32)0x1CU))

#define RCM_APBCLKEN1_TMR2EN_MASK        ((uint32)0x00000001U)
#define RCM_APBCLKEN1_TMR2EN_SHIFT       ((uint8)0U)

#define RCM_APBCLKEN1_TMR3EN_MASK        ((uint32)0x00000002U)
#define RCM_APBCLKEN1_TMR3EN_SHIFT       ((uint8)1U)

#define RCM_APBCLKEN1_TMR4EN_MASK        ((uint32)0x00000004U)
#define RCM_APBCLKEN1_TMR4EN_SHIFT       ((uint8)2U)

#define RCM_APBCLKEN1_TMR6EN_MASK        ((uint32)0x00000010U)
#define RCM_APBCLKEN1_TMR6EN_SHIFT       ((uint8)4U)

#define RCM_APBCLKEN1_TMR7EN_MASK        ((uint32)0x00000020U)
#define RCM_APBCLKEN1_TMR7EN_SHIFT       ((uint8)5U)

#define RCM_APBCLKEN1_USART2EN_MASK      ((uint32)0x00020000U)
#define RCM_APBCLKEN1_USART2EN_SHIFT     ((uint8)17U)

#define RCM_APBCLKEN1_CANEN_MASK         ((uint32)0x02000000U)
#define RCM_APBCLKEN1_CANEN_SHIFT        ((uint8)25U)

#define RCM_APBCLKEN1_PMUEN_MASK         ((uint32)0x10000000U)
#define RCM_APBCLKEN1_PMUEN_SHIFT        ((uint8)28U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_RTCCTRL (Base + 0x20)
************************************************************************************************************/
/** RCM_RTCCTRL register address */
#define RCM_RTCCTRL_REG_ADDR             ((uint32)(RCM_BASEADDR + (uint32)0x20U))

#define RCM_RTCCTRL_RTCSRCSEL_MASK       ((uint32)0x00000300U)
#define RCM_RTCCTRL_RTCSRCSEL_SHIFT      ((uint8)8U)

#define RCM_RTCCTRL_RTCCLKEN_MASK        ((uint32)0x00008000U)
#define RCM_RTCCTRL_RTCCLKEN_SHIFT       ((uint8)15U)

#define RCM_RTCCTRL_RTCRST_MASK          ((uint32)0x00010000U)
#define RCM_RTCCTRL_RTCRST_SHIFT         ((uint8)16U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_CSTS (Base + 0x24)
************************************************************************************************************/
/** RCM_CSTS register address */
#define RCM_CSTS_REG_ADDR                ((uint32)(RCM_BASEADDR + (uint32)0x24U))

#define RCM_CSTS_LSIEN_MASK              ((uint32)0x00000001U)
#define RCM_CSTS_LSIEN_SHIFT             ((uint8)0U)

#define RCM_CSTS_LSIRDYFLG_MASK          ((uint32)0x00000002U)
#define RCM_CSTS_LSIRDYFLG_SHIFT         ((uint8)1U)

#define RCM_CSTS_LOCRSTFLG_MASK          ((uint32)0x00400000U)
#define RCM_CSTS_LOCRSTFLG_SHIFT         ((uint8)22U)

#define RCM_CSTS_PWRRSTFLG_MASK          ((uint32)0x00800000U)
#define RCM_CSTS_PWRRSTFLG_SHIFT         ((uint8)23U)

#define RCM_CSTS_RSTFLGCLR_MASK          ((uint32)0x01000000U)
#define RCM_CSTS_RSTFLGCLR_SHIFT         ((uint8)24U)

#define RCM_CSTS_OBRSTFLG_MASK           ((uint32)0x02000000U)
#define RCM_CSTS_OBRSTFLG_SHIFT          ((uint8)25U)

#define RCM_CSTS_PINRSTFLG_MASK          ((uint32)0x04000000U)
#define RCM_CSTS_PINRSTFLG_SHIFT         ((uint8)26U)

#define RCM_CSTS_PODRSTFLG_MASK          ((uint32)0x08000000U)
#define RCM_CSTS_PODRSTFLG_SHIFT         ((uint8)27U)

#define RCM_CSTS_SWRSTFLG_MASK           ((uint32)0x10000000U)
#define RCM_CSTS_SWRSTFLG_SHIFT          ((uint8)28U)

#define RCM_CSTS_IWDTRSTFLG_MASK         ((uint32)0x20000000U)
#define RCM_CSTS_IWDTRSTFLG_SHIFT        ((uint8)29U)

#define RCM_CSTS_LPWRRSTFLG_MASK         ((uint32)0x80000000U)
#define RCM_CSTS_LPWRRSTFLG_SHIFT        ((uint8)31U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_AHBRST (Base + 0x28)
************************************************************************************************************/
/** RCM_AHBRST register address */
#define RCM_AHBRST_REG_ADDR              ((uint32)(RCM_BASEADDR + (uint32)0x28U))

#define RCM_AHBRST_TRNGRST_MASK          ((uint32)0x00000080U)
#define RCM_AHBRST_TRNGRST_SHIFT         ((uint8)7U)

#define RCM_AHBRST_SHARST_MASK           ((uint32)0x00000100U)
#define RCM_AHBRST_SHARST_SHIFT          ((uint8)8U)

#define RCM_AHBRST_AES256RST_MASK        ((uint32)0x00000200U)
#define RCM_AHBRST_AES256RST_SHIFT       ((uint8)9U)

#define RCM_AHBRST_PARST_MASK            ((uint32)0x00020000U)
#define RCM_AHBRST_PARST_SHIFT           ((uint8)17U)

#define RCM_AHBRST_PBRST_MASK            ((uint32)0x00040000U)
#define RCM_AHBRST_PBRST_SHIFT           ((uint8)18U)

#define RCM_AHBRST_PCRST_MASK            ((uint32)0x00080000U)
#define RCM_AHBRST_PCRST_SHIFT           ((uint8)19U)

#define RCM_AHBRST_PDRST_MASK            ((uint32)0x00100000U)
#define RCM_AHBRST_PDRST_SHIFT           ((uint8)20U)

#define RCM_AHBRST_PFRST_MASK            ((uint32)0x00400000U)
#define RCM_AHBRST_PFRST_SHIFT           ((uint8)22U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_CFG2 (Base + 0x2C)
************************************************************************************************************/
/** RCM_CFG2 register address */
#define RCM_CFG2_REG_ADDR                ((uint32)(RCM_BASEADDR + (uint32)0x2CU))

#define RCM_CFG2_PLLDIVCFG_MASK          ((uint32)0x0000000FU)
#define RCM_CFG2_PLLDIVCFG_SHIFT         ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_CFG3 (Base + 0x30)
************************************************************************************************************/
/** RCM_CFG3 register address */
#define RCM_CFG3_REG_ADDR                ((uint32)(RCM_BASEADDR + (uint32)0x30U))

#define RCM_CFG3_USART1SEL_MASK          ((uint32)0x00000003U)
#define RCM_CFG3_USART1SEL_SHIFT         ((uint8)0U)

#define RCM_CFG3_USART2SEL_MASK          ((uint32)0x0000000CU)
#define RCM_CFG3_USART2SEL_SHIFT         ((uint8)2U)

#define RCM_CFG3_CANFDSEL_MASK           ((uint32)0x00001000U)
#define RCM_CFG3_CANFDSEL_SHIFT          ((uint8)12U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_CTRL2 (Base + 0x34)
************************************************************************************************************/
/** RCM_CTRL2 register address */
#define RCM_CTRL2_REG_ADDR               ((uint32)(RCM_BASEADDR + (uint32)0x34U))

#define RCM_CTRL2_HSI14EN_MASK           ((uint32)0x00000001U)
#define RCM_CTRL2_HSI14EN_SHIFT          ((uint8)0U)

#define RCM_CTRL2_HSI14RDFLG_MASK        ((uint32)0x00000002U)
#define RCM_CTRL2_HSI14RDFLG_SHIFT       ((uint8)1U)

#define RCM_CTRL2_HSI14TO_MASK           ((uint32)0x00000004U)
#define RCM_CTRL2_HSI14TO_SHIFT          ((uint8)2U)

#define RCM_CTRL2_HSI14TRM_MASK          ((uint32)0x000000F8U)
#define RCM_CTRL2_HSI14TRM_SHIFT         ((uint8)3U)

#define RCM_CTRL2_HSI14CAL_MASK          ((uint32)0x0000FF00U)
#define RCM_CTRL2_HSI14CAL_SHIFT         ((uint8)8U)

#define RCM_CTRL2_LSITRM_MASK            ((uint32)0x00FC0000U)
#define RCM_CTRL2_LSITRM_SHIFT           ((uint8)18U)

#define RCM_CTRL2_LSICAL_MASK            ((uint32)0xFF000000U)
#define RCM_CTRL2_LSICAL_SHIFT           ((uint8)24U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_INT2 (Base + 0x40)
************************************************************************************************************/
/** RCM_INT2 register address */
#define RCM_INT2_REG_ADDR                ((uint32)(RCM_BASEADDR + (uint32)0x40U))

#define RCM_INT2_FLLFLG_MASK             ((uint32)0x00000001U)
#define RCM_INT2_FLLFLG_SHIFT            ((uint8)0U)

#define RCM_INT2_FHHFLG_MASK             ((uint32)0x00000002U)
#define RCM_INT2_FHHFLG_SHIFT            ((uint8)1U)

#define RCM_INT2_LOCFLG_MASK             ((uint32)0x00000004U)
#define RCM_INT2_LOCFLG_SHIFT            ((uint8)2U)

#define RCM_INT2_FLLIE_MASK              ((uint32)0x00000100U)
#define RCM_INT2_FLLIE_SHIFT             ((uint8)8U)

#define RCM_INT2_FHHIE_MASK              ((uint32)0x00000200U)
#define RCM_INT2_FHHIE_SHIFT             ((uint8)9U)

#define RCM_INT2_LOCIE_MASK              ((uint32)0x00000400U)
#define RCM_INT2_LOCIE_SHIFT             ((uint8)10U)

#define RCM_INT2_FLLCLR_MASK             ((uint32)0x00010000U)
#define RCM_INT2_FLLCLR_SHIFT            ((uint8)16U)

#define RCM_INT2_FHHCLR_MASK             ((uint32)0x00020000U)
#define RCM_INT2_FHHCLR_SHIFT            ((uint8)17U)

#define RCM_INT2_LOCCLR_MASK             ((uint32)0x00040000U)
#define RCM_INT2_LOCCLR_SHIFT            ((uint8)18U)

#define RCM_INT2_SLOCEN_MASK             ((uint32)0x04000000U)
#define RCM_INT2_SLOCEN_SHIFT            ((uint8)26U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_CFG4 (Base + 0x44)
************************************************************************************************************/
/** RCM_CFG4 register address */
#define RCM_CFG4_REG_ADDR                ((uint32)(RCM_BASEADDR + (uint32)0x44U))

#define RCM_CFG4_CMU_EN_MASK             ((uint32)0x00000001U)
#define RCM_CFG4_CMU_EN_SHIFT            ((uint8)0U)

#define RCM_CFG4_CLK_SEL_MASK            ((uint32)0x00000002U)
#define RCM_CFG4_CLK_SEL_SHIFT           ((uint8)1U)

#define RCM_CFG4_FLL_MASK                ((uint32)0x00000100U)
#define RCM_CFG4_FLL_SHIFT               ((uint8)8U)

#define RCM_CFG4_FHH_MASK                ((uint32)0x00000200U)
#define RCM_CFG4_FHH_SHIFT               ((uint8)9U)

#define RCM_CFG4_LOC_MASK                ((uint32)0x00000400U)
#define RCM_CFG4_LOC_SHIFT               ((uint8)10U)

#define RCM_CFG4_VLD_MASK                ((uint32)0x00000800U)
#define RCM_CFG4_VLD_SHIFT               ((uint8)11U)

#define RCM_CFG4_REFPRE_MASK             ((uint32)0x003F0000U)
#define RCM_CFG4_REFPRE_SHIFT            ((uint8)16U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_REF_CNT (Base + 0x48)
************************************************************************************************************/
/** RCM_REF_CNT register address */
#define RCM_REF_CNT_REG_ADDR             ((uint32)(RCM_BASEADDR + (uint32)0x48U))

#define RCM_REF_CNT_MASK                 ((uint32)0x0000003FU)
#define RCM_REF_CNT_SHIFT                ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_MEAS (Base + 0x4C)
************************************************************************************************************/
/** RCM_MEAS register address */
#define RCM_MEAS_REG_ADDR                ((uint32)(RCM_BASEADDR + (uint32)0x4CU))

#define RCM_MEAS_VAL_MASK                ((uint32)0x0000FFFFU)
#define RCM_MEAS_VAL_SHIFT               ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_FHCR (Base + 0x50)
************************************************************************************************************/
/** RCM_FHCR register address */
#define RCM_FHCR_REG_ADDR                ((uint32)(RCM_BASEADDR + (uint32)0x50U))

#define RCM_FH_VAL_MASK                  ((uint32)0x0000FFFFU)
#define RCM_FH_VAL_SHIFT                 ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RCM_FLCR (Base + 0x54)
************************************************************************************************************/
/** RCM_FLCR register address */
#define RCM_FLCR_REG_ADDR                ((uint32)(RCM_BASEADDR + (uint32)0x54U))

#define RCM_FL_VAL_MASK                  ((uint32)0x0000FFFFU)
#define RCM_FL_VAL_SHIFT                 ((uint8)0U)

/**@} end of group MCU_Macros */

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* MCU_RCM_REG_H */

/**@} end of group MCU_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
