/*!
* @file     Mcu_SysCfgReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the SYSCFG module.
*
* @details  This header file includes the register definitions of the SYSCFG module.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef MCU_SYSCFGREG_H
#define MCU_SYSCFGREG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @addtogroup MCU_Driver
  @{
*/

/** @defgroup MCU_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define MCU_SYSCFG_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define MCU_SYSCFG_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_SYSCFG_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_SYSCFG_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define MCU_SYSCFG_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_SYSCFG_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_SYSCFG_REG_H_SW_PATCH_VERSION                        0x00U

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Mcu_SysCfgReg.h and Reg_eSys.h */
    #if (MCU_SYSCFG_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Mcu_SysCfgReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Mcu_SysCfgReg.h and Reg_eSys.h */
    #if (MCU_SYSCFG_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Mcu_SysCfgReg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
                                            MACRO DEFINITION
************************************************************************************************************/


/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SYSCFG_CFG1 (Base + 0x00)
************************************************************************************************************/
/** SYSCFG_CFG1 register address */
#define SYSCFG_CFG1_REG_ADDR                ((uint32)(SYSCFG_BASEADDR + (uint32)0U))

#define SYSCFG_CFG1_MMSEL_MASK              ((uint32)0x00000003U)
#define SYSCFG_CFG1_MMSEL_SHIFT             ((uint8)0U)

#define SYSCFG_CFG1_ADCDMARMP_MASK          ((uint32)0x00000100U)
#define SYSCFG_CFG1_ADCDMARMP_SHIFT         ((uint8)8U)

#define SYSCFG_CFG1_USART1TXRMP_MASK        ((uint32)0x00000200U)
#define SYSCFG_CFG1_USART1TXRMP_SHIFT       ((uint8)9U)

#define SYSCFG_CFG1_USART1RXRMP_MASK        ((uint32)0x00000400U)
#define SYSCFG_CFG1_USART1RXRMP_SHIFT       ((uint8)10U)

#define SYSCFG_CFG1_TIM4CH3RMP_MASK         ((uint32)0x00010000U)
#define SYSCFG_CFG1_TIM4CH3RMP_SHIFT        ((uint8)16U)

#define SYSCFG_CFG1_TIM4UPRMP_MASK          ((uint32)0x00020000U)
#define SYSCFG_CFG1_TIM4UPRMP_SHIFT         ((uint8)17U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SYSCFG_EINTCFG1 (Base + 0x08)
************************************************************************************************************/
/** SYSCFG_EINTCFG1 register address */
#define SYSCFG_EINTCFG1_REG_ADDR            ((uint32)(SYSCFG_BASEADDR + (uint32)0x08U))

#define SYSCFG_EINTCFG1_EINT0_MASK          ((uint32)0x0000000FU)
#define SYSCFG_EINTCFG1_EINT0_SHIFT         ((uint8)0U)

#define SYSCFG_EINTCFG1_EINT1_MASK          ((uint32)0x000000F0U)
#define SYSCFG_EINTCFG1_EINT1_SHIFT         ((uint8)4U)

#define SYSCFG_EINTCFG1_EINT2_MASK          ((uint32)0x00000F00U)
#define SYSCFG_EINTCFG1_EINT2_SHIFT         ((uint8)8U)

#define SYSCFG_EINTCFG1_EINT3_MASK          ((uint32)0x0000F000U)
#define SYSCFG_EINTCFG1_EINT3_SHIFT         ((uint8)12U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SYSCFG_EINTCFG2 (Base + 0x0C)
************************************************************************************************************/
/** SYSCFG_EINTCFG2 register address */
#define SYSCFG_EINTCFG2_REG_ADDR            ((uint32)(SYSCFG_BASEADDR + (uint32)0x0CU))

#define SYSCFG_EINTCFG2_EINT4_MASK          ((uint32)0x0000000FU)
#define SYSCFG_EINTCFG2_EINT4_SHIFT         ((uint8)0U)

#define SYSCFG_EINTCFG2_EINT5_MASK          ((uint32)0x000000F0U)
#define SYSCFG_EINTCFG2_EINT5_SHIFT         ((uint8)4U)

#define SYSCFG_EINTCFG2_EINT6_MASK          ((uint32)0x00000F00U)
#define SYSCFG_EINTCFG2_EINT6_SHIFT         ((uint8)8U)

#define SYSCFG_EINTCFG2_EINT7_MASK          ((uint32)0x0000F000U)
#define SYSCFG_EINTCFG2_EINT7_SHIFT         ((uint8)12U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SYSCFG_EINTCFG3 (Base + 0x10)
************************************************************************************************************/
/** SYSCFG_EINTCFG3 register address */
#define SYSCFG_EINTCFG3_REG_ADDR            ((uint32)(SYSCFG_BASEADDR + (uint32)0x10U))

#define SYSCFG_EINTCFG3_EINT8_MASK          ((uint32)0x0000000FU)
#define SYSCFG_EINTCFG3_EINT8_SHIFT         ((uint8)0U)

#define SYSCFG_EINTCFG3_EINT9_MASK          ((uint32)0x000000F0U)
#define SYSCFG_EINTCFG3_EINT9_SHIFT         ((uint8)4U)

#define SYSCFG_EINTCFG3_EINT10_MASK         ((uint32)0x00000F00U)
#define SYSCFG_EINTCFG3_EINT10_SHIFT        ((uint8)8U)

#define SYSCFG_EINTCFG3_EINT11_MASK         ((uint32)0x0000F000U)
#define SYSCFG_EINTCFG3_EINT11_SHIFT        ((uint8)12U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SYSCFG_EINTCFG4 (Base + 0x14)
************************************************************************************************************/
/** SYSCFG_EINTCFG4 register address */
#define SYSCFG_EINTCFG4_REG_ADDR            ((uint32)(SYSCFG_BASEADDR + (uint32)0x14U))

#define SYSCFG_EINTCFG4_EINT12_MASK         ((uint32)0x0000000FU)
#define SYSCFG_EINTCFG4_EINT12_SHIFT        ((uint8)0U)

#define SYSCFG_EINTCFG4_EINT13_MASK         ((uint32)0x000000F0U)
#define SYSCFG_EINTCFG4_EINT13_SHIFT        ((uint8)4U)

#define SYSCFG_EINTCFG4_EINT14_MASK         ((uint32)0x00000F00U)
#define SYSCFG_EINTCFG4_EINT14_SHIFT        ((uint8)8U)

#define SYSCFG_EINTCFG4_EINT15_MASK         ((uint32)0x0000F000U)
#define SYSCFG_EINTCFG4_EINT15_SHIFT        ((uint8)12U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: SYSCFG_CFG2 (Base + 0x18)
************************************************************************************************************/
/** SYSCFG_CFG2 register address */
#define SYSCFG_CFG2_REG_ADDR                ((uint32)(SYSCFG_BASEADDR + (uint32)0x18U))

#define SYSCFG_CFG2_LOCK_MASK               ((uint32)0x00000001U)
#define SYSCFG_CFG2_LOCK_SHIFT              ((uint8)0U)

#define SYSCFG_CFG2_PVDLOCK_MASK            ((uint32)0x00000004U)
#define SYSCFG_CFG2_PVDLOCK_SHIFT           ((uint8)2U)

/**@} end of group MCU_Macros */

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* MCU_SYSCFG_REG_H */

/**@} end of group MCU_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
