/*!
* @file     Fls_FmcReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the FMC module
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef FLS_FMC_REG_H
#define FLS_FMC_REG_H

#ifdef __cplusplus
extern "C"{
#endif

#include "Reg_eSys.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup FLS_Driver
  * @brief FLS driver modules
  @{
*/

/** @defgroup FLS_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
***********************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define FLS_FMC_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define FLS_FMC_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define FLS_FMC_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define FLS_FMC_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define FLS_FMC_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define FLS_FMC_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define FLS_FMC_REG_H_SW_PATCH_VERSION                        0x00U

/**@} end of group FLS_Macros */

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
***********************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Fls_FmcReg.h and Reg_eSys.h */
    #if (FLS_FMC_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Fls_FmcReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Fls_FmcReg.h and Reg_eSys.h */
    #if (FLS_FMC_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Fls_FmcReg.h and Reg_eSys.h"
    #endif
#endif

/** @defgroup FLS_Macros
  @{
*/

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_CTRL1 (Base + 0x00)
************************************************************************************************************/
#define FMC_CTRL1_REG_ADDR               ((uint32)(FMC_BASEADDR + (uint32)0x00U))

#define FMC_CTRL1_WS_MASK                ((uint32)0x0000000FU)
#define FMC_CTRL1_WS_SHIFT               ((uint8)0U)

#define FMC_CTRL1_PBEN_MASK              ((uint32)0x00000010U)
#define FMC_CTRL1_PBEN_SHIFT             ((uint8)4U)

#define FMC_CTRL1_PBSF_MASK              ((uint32)0x00000020U)
#define FMC_CTRL1_PBSF_SHIFT             ((uint8)5U)

#define FMC_CTRL1_VREAD0_EN_MASK         ((uint32)0x00000100U)
#define FMC_CTRL1_VREAD0_EN_SHIFT        ((uint8)8U)

#define FMC_CTRL1_VREAD0_STS_MASK        ((uint32)0x00000200U)
#define FMC_CTRL1_VREAD0_STS_SHIFT       ((uint8)9U)

#define FMC_CTRL1_VREAD1_EN_MASK         ((uint32)0x00001000U)
#define FMC_CTRL1_VREAD1_EN_SHIFT        ((uint8)12U)

#define FMC_CTRL1_VREAD1_STS_MASK        ((uint32)0x00002000U)
#define FMC_CTRL1_VREAD1_STS_SHIFT       ((uint8)13U)

#define FMC_CTRL1_ECCEN_MASK             ((uint32)0x00010000U)
#define FMC_CTRL1_ECCEN_SHIFT            ((uint8)16U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_KEY (Base + 0x04)
************************************************************************************************************/
#define FMC_KEY_REG_ADDR                 ((uint32)(FMC_BASEADDR + (uint32)0x04U))

#define FMC_KEY_MASK                     ((uint32)0xFFFFFFFFU)
#define FMC_KEY_SHIFT                    ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OBKEY (Base + 0x08)
************************************************************************************************************/
#define FMC_OBKEY_REG_ADDR               ((uint32)(FMC_BASEADDR + (uint32)0x08U))

#define FMC_OBKEY_MASK                   ((uint32)0xFFFFFFFFU)
#define FMC_OBKEY_SHIFT                  ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_STS (Base + 0x0C)
************************************************************************************************************/
#define FMC_STS_REG_ADDR                 ((uint32)(FMC_BASEADDR + (uint32)0x0CU))

#define FMC_STS_BUSYF_MASK               ((uint32)0x00000001U)
#define FMC_STS_BUSYF_SHIFT              ((uint8)0U)

#define FMC_STS_PEF_MASK                 ((uint32)0x00000004U)
#define FMC_STS_PEF_SHIFT                ((uint8)2U)

#define FMC_STS_PAEF_MASK                ((uint32)0x00000008U)
#define FMC_STS_PAEF_SHIFT               ((uint8)3U)

#define FMC_STS_WPEF_MASK                ((uint32)0x00000010U)
#define FMC_STS_WPEF_SHIFT               ((uint8)4U)

#define FMC_STS_OCF_MASK                 ((uint32)0x00000020U)
#define FMC_STS_OCF_SHIFT                ((uint8)5U)

#define FMC_STS_DBFIFLG_MASK             ((uint32)0x00010000U)
#define FMC_STS_DBFIFLG_SHIFT            ((uint8)16U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_CTRL2 (Base + 0x10)
************************************************************************************************************/
#define FMC_CTRL2_REG_ADDR               ((uint32)(FMC_BASEADDR + (uint32)0x10U))

#define FMC_CTRL2_PG_MASK                ((uint32)0x00000001U)
#define FMC_CTRL2_PG_SHIFT               ((uint8)0U)

#define FMC_CTRL2_PAGEERA_MASK           ((uint32)0x00000002U)
#define FMC_CTRL2_PAGEERA_SHIFT          ((uint8)1U)

#define FMC_CTRL2_MASSERA_MASK           ((uint32)0x00000004U)
#define FMC_CTRL2_MASSERA_SHIFT          ((uint8)2U)

#define FMC_CTRL2_OBP_MASK               ((uint32)0x00000010U)
#define FMC_CTRL2_OBP_SHIFT              ((uint8)4U)

#define FMC_CTRL2_OBE_MASK               ((uint32)0x00000020U)
#define FMC_CTRL2_OBE_SHIFT              ((uint8)5U)

#define FMC_CTRL2_STA_MASK               ((uint32)0x00000040U)
#define FMC_CTRL2_STA_SHIFT              ((uint8)6U)

#define FMC_CTRL2_LOCK_MASK              ((uint32)0x00000080U)
#define FMC_CTRL2_LOCK_SHIFT             ((uint8)7U)

#define FMC_CTRL2_OBWEN_MASK             ((uint32)0x00000200U)
#define FMC_CTRL2_OBWEN_SHIFT            ((uint8)9U)

#define FMC_CTRL2_ERRIE_MASK             ((uint32)0x00000400U)
#define FMC_CTRL2_ERRIE_SHIFT            ((uint8)10U)

#define FMC_CTRL2_OCIE_MASK              ((uint32)0x00001000U)
#define FMC_CTRL2_OCIE_SHIFT             ((uint8)12U)

#define FMC_CTRL2_OBLOAD_MASK            ((uint32)0x00002000U)
#define FMC_CTRL2_OBLOAD_SHIFT           ((uint8)13U)

#define FMC_CTRL2_DBFIEN_MASK            ((uint32)0x00010000U)
#define FMC_CTRL2_DBFIEN_SHIFT           ((uint8)16U)

#define FMC_CTRL2_OBRIE_MASK             ((uint32)0x00020000U)
#define FMC_CTRL2_OBRIE_SHIFT            ((uint8)17U)

#define FMC_CTRL2_MER_TYPE_MASK          ((uint32)0x000C0000U)
#define FMC_CTRL2_MER_TYPE_SHIFT         ((uint8)18U)

#define FMC_CTRL2_PROGLEN_MASK           ((uint32)0x00300000U)
#define FMC_CTRL2_PROGLEN_SHIFT          ((uint8)20U)

#define FMC_CTRL2_SCR_MASK               ((uint32)0xFF000000U)
#define FMC_CTRL2_SCR_SHIFT              ((uint8)24U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_ADDR (Base + 0x14)
************************************************************************************************************/
#define FMC_ADDR_REG_ADDR                ((uint32)(FMC_BASEADDR + (uint32)0x14U))

#define FMC_ADDR_MASK                    ((uint32)0xFFFFFFFFU)
#define FMC_ADDR_SHIFT                   ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OBCS (Base + 0x1C)
************************************************************************************************************/
#define FMC_OBCS_REG_ADDR                ((uint32)(FMC_BASEADDR + (uint32)0x1CU))

#define FMC_OBCS_OBE_MASK                ((uint32)0x00000001U)
#define FMC_OBCS_OBE_SHIFT               ((uint8)0U)

#define FMC_OBCS_READPROT_MASK           ((uint32)0x00000006U)
#define FMC_OBCS_READPROT_SHIFT          ((uint8)1U)

#define FMC_OBCS_SCRKERR_MASK            ((uint32)0x00000008U)
#define FMC_OBCS_SCRKERR_SHIFT           ((uint8)3U)

#define FMC_OBCS_SCRECCERR_MASK          ((uint32)0x00000010U)
#define FMC_OBCS_SCRECCERR_SHIFT         ((uint8)4U)

#define FMC_OBCS_OPTRERR_MASK            ((uint32)0x00000020U)
#define FMC_OBCS_OPTRERR_SHIFT           ((uint8)5U)

#define FMC_OBCS_OPTECCERR_MASK          ((uint32)0x00000040U)
#define FMC_OBCS_OPTECCERR_SHIFT         ((uint8)6U)

#define FMC_OBCS_WDTSEL_MASK             ((uint32)0x00000100U)
#define FMC_OBCS_WDTSEL_SHIFT            ((uint8)8U)

#define FMC_OBCS_RSTSTOP_MASK            ((uint32)0x00000200U)
#define FMC_OBCS_RSTSTOP_SHIFT           ((uint8)9U)

#define FMC_OBCS_RSTSTDB_MASK            ((uint32)0x00000400U)
#define FMC_OBCS_RSTSTDB_SHIFT           ((uint8)10U)

#define FMC_OBCS_NBOOT0_MASK             ((uint32)0x00000800U)
#define FMC_OBCS_NBOOT0_SHIFT            ((uint8)11U)

#define FMC_OBCS_NBOOT1_MASK             ((uint32)0x00001000U)
#define FMC_OBCS_NBOOT1_SHIFT            ((uint8)12U)

#define FMC_OBCS_VDDAMONI_MASK           ((uint32)0x00002000U)
#define FMC_OBCS_VDDAMONI_SHIFT          ((uint8)13U)

#define FMC_OBCS_DATA0_MASK              ((uint32)0x00FF0000U)
#define FMC_OBCS_DATA0_SHIFT             ((uint8)16U)

#define FMC_OBCS_DATA1_MASK              ((uint32)0xFF000000U)
#define FMC_OBCS_DATA1_SHIFT             ((uint8)24U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_WRTPROT0 (Base + 0x20)
************************************************************************************************************/
#define FMC_WRTPROT0_REG_ADDR            ((uint32)(FMC_BASEADDR + (uint32)0x20U))

#define FMC_WRTPROT0_MASK                ((uint32)0xFFFFFFFFU)
#define FMC_WRTPROT0_SHIFT               ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_WRTPROT1 (Base + 0x24)
************************************************************************************************************/
#define FMC_WRTPROT1_REG_ADDR            ((uint32)(FMC_BASEADDR + (uint32)0x24U))

#define FMC_WRTPROT1_MASK                ((uint32)0xFFFFFFFFU)
#define FMC_WRTPROT1_SHIFT               ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_ECC_ADDR (Base + 0x30)
************************************************************************************************************/
#define FMC_ECC_ADDR_REG_ADDR            ((uint32)(FMC_BASEADDR + (uint32)0x30U))

#define FMC_ECC_ADDR_MASK                ((uint32)0xFFFFFFFFU)
#define FMC_ECC_ADDR_SHIFT               ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_PROG_DATA (Base + 0x40 + 0x04 * N)
************************************************************************************************************/
/** The value of NUM is an integer between 0 and 15, inclusive of 0 and 15 */
#define FMC_PROG_DATA_REG_ADDR(NUM)      ((uint32)(FMC_BASEADDR + (uint32)0x40U + ((uint32)0x04U * NUM)))

#define FMC_PROG_DATA_MASK               ((uint32)0xFFFFFFFFU)
#define FMC_PROG_DATA_SHIFT              ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_READPROT (Base + 0x00)
************************************************************************************************************/
#define FMC_OPT_READPROT_REG_ADDR        ((uint32)(FMC_OPT_BASEADDR + (uint32)0x00U))

#define FMC_OPT_READPROT_MASK            ((uint8)0xFFU)
#define FMC_OPT_READPROT_SHIFT           ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_NREADPROT (Base + 0x01)
************************************************************************************************************/
#define FMC_OPT_NREADPROT_REG_ADDR       ((uint32)(FMC_OPT_BASEADDR + (uint32)0x01U))

#define FMC_OPT_NREADPROT_MASK           ((uint8)0xFFU)
#define FMC_OPT_NREADPROT_SHIFT          ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_UOB (Base + 0x02)
************************************************************************************************************/
#define FMC_OPT_UOB_REG_ADDR             ((uint32)(FMC_OPT_BASEADDR + (uint32)0x02U))

#define FMC_OPT_UOB_MASK                 ((uint8)0xFFU)
#define FMC_OPT_UOB_SHIFT                ((uint8)0U)

#define FMC_OPT_UOB_WDTSEL_MASK          ((uint8)0x01U)
#define FMC_OPT_UOB_WDTSEL_SHIFT         ((uint8)0U)

#define FMC_OPT_UOB_NRSTSTOP_MASK        ((uint8)0x02U)
#define FMC_OPT_UOB_NRSTSTOP_SHIFT       ((uint8)1U)

#define FMC_OPT_UOB_NRSTSTANDBY_MASK     ((uint8)0x04U)
#define FMC_OPT_UOB_NRSTSTANDBY_SHIFT    ((uint8)2U)

#define FMC_OPT_UOB_NBOOT0_MASK          ((uint8)0x08U)
#define FMC_OPT_UOB_NBOOT0_SHIFT         ((uint8)3U)

#define FMC_OPT_UOB_NBOOT1_MASK          ((uint8)0x10U)
#define FMC_OPT_UOB_NBOOT1_SHIFT         ((uint8)4U)

#define FMC_OPT_UOB_VDDA_MONITOR_MASK    ((uint8)0x20U)
#define FMC_OPT_UOB_VDDA_MONITOR_SHIFT   ((uint8)5U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_NUOB (Base + 0x03)
************************************************************************************************************/
#define FMC_OPT_NUOB_REG_ADDR            ((uint32)(FMC_OPT_BASEADDR + (uint32)0x03U))

#define FMC_OPT_NUOB_MASK                ((uint8)0xFFU)
#define FMC_OPT_NUOB_SHIFT               ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_DATA0 (Base + 0x04)
************************************************************************************************************/
#define FMC_OPT_DATA0_REG_ADDR           ((uint32)(FMC_OPT_BASEADDR + (uint32)0x04U))

#define FMC_OPT_DATA0_MASK               ((uint8)0xFFU)
#define FMC_OPT_DATA0_SHIFT              ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_NDATA0 (Base + 0x05)
************************************************************************************************************/
#define FMC_OPT_NDATA0_REG_ADDR          ((uint32)(FMC_OPT_BASEADDR + (uint32)0x05U))

#define FMC_OPT_NDATA0_MASK              ((uint8)0xFFU)
#define FMC_OPT_NDATA0_SHIFT             ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_DATA1 (Base + 0x06)
************************************************************************************************************/
#define FMC_OPT_DATA1_REG_ADDR           ((uint32)(FMC_OPT_BASEADDR + (uint32)0x06U))

#define FMC_OPT_DATA1_MASK               ((uint8)0xFFU)
#define FMC_OPT_DATA1_SHIFT              ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_NDATA1 (Base + 0x07)
************************************************************************************************************/
#define FMC_OPT_NDATA1_REG_ADDR          ((uint32)(FMC_OPT_BASEADDR + (uint32)0x07U))

#define FMC_OPT_NDATA1_MASK              ((uint8)0xFFU)
#define FMC_OPT_NDATA1_SHIFT             ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_WRP (Base + 0x08 + 0x02 * NUM)
************************************************************************************************************/
/** The value of NUM is an integer between 0 and 7, inclusive of 0 and 7 */
#define FMC_OPT_WRP_REG_ADDR(NUM)        ((uint32)(FMC_OPT_BASEADDR + (uint32)0x08U + ((uint32)0x02U * NUM)))

#define FMC_OPT_WRP_MASK                 ((uint8)0xFFU)
#define FMC_OPT_WRP_SHIFT                ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: FMC_OPT_NWRP (Base + 0x09 + 0x02 * NUM)
************************************************************************************************************/
/** The value of NUM is an integer between 0 and 7, inclusive of 0 and 7 */
#define FMC_OPT_NWRP_REG_ADDR(NUM)       ((uint32)(FMC_OPT_BASEADDR + (uint32)0x09U + ((uint32)0x02U * NUM)))

#define FMC_OPT_NWRP_MASK                ((uint8)0xFFU)
#define FMC_OPT_NWRP_SHIFT               ((uint8)0U)

/**@} end of group FLS_Macros */

#ifdef __cplusplus
}
#endif

#endif

/**@} end of group FLS_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
