/*!
* @file     Mcu_DbgMcuReg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the debug MCU(DBGMCU) module.
*
* @details  This header file includes the register definitions of the debug MCU(DBGMCU) module.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef MCU_DBGMCUREG_H
#define MCU_DBGMCUREG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @addtogroup MCU_Driver
  @{
*/

/** @defgroup MCU_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
***********************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define MCU_DBGMCU_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define MCU_DBGMCU_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_DBGMCU_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_DBGMCU_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define MCU_DBGMCU_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_DBGMCU_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_DBGMCU_REG_H_SW_PATCH_VERSION                        0x00U

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
***********************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Mcu_DbgMcuReg.h and Reg_eSys.h */
    #if (MCU_DBGMCU_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Mcu_DbgMcuReg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Mcu_DbgMcuReg.h and Reg_eSys.h */
    #if (MCU_DBGMCU_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Mcu_DbgMcuReg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DBGMCU_IDCODE (Base + 0x00)
************************************************************************************************************/
/** DBGMCU_IDCODE register address */
#define DBGMCU_IDCODE_REG_ADDR           ((uint32)(DBGMCU_BASEADDR + (uint32)0x00U))

#define DBGMCU_IDCODE_EQR_MASK           ((uint32)0x00000FFFU)
#define DBGMCU_IDCODE_EQR_SHIFT          ((uint8)0U)

#define DBGMCU_IDCODE_WVR_MASK           ((uint32)0xFFFF0000U)
#define DBGMCU_IDCODE_WVR_SHIFT          ((uint8)16U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DBGMCU_CFG (Base + 0x04)
************************************************************************************************************/
/** DBGMCU_CFG register address */
#define DBGMCU_CFG_REG_ADDR                 ((uint32)(DBGMCU_BASEADDR + (uint32)0x04U))

#define DBGMCU_CFG_STOP_CLK_STS_MASK        ((uint32)0x00000002U)
#define DBGMCU_CFG_STOP_CLK_STS_SHIFT       ((uint8)1U)

#define DBGMCU_CFG_STANDBY_CLK_STS_MASK     ((uint32)0x00000004U)
#define DBGMCU_CFG_STANDBY_CLK_STS_SHIFT    ((uint8)2U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DBGMCU_APB1F (Base + 0x08)
************************************************************************************************************/
/** DBGMCU_APB1F register address */
#define DBGMCU_APB1F_REG_ADDR            ((uint32)(DBGMCU_BASEADDR + (uint32)0x08U))

#define DBGMCU_APB1F_TMR2_STS_MASK       ((uint32)0x00000001U)
#define DBGMCU_APB1F_TMR2_STS_SHIFT      ((uint8)0U)

#define DBGMCU_APB1F_TMR3_STS_MASK       ((uint32)0x00000002U)
#define DBGMCU_APB1F_TMR3_STS_SHIFT      ((uint8)1U)

#define DBGMCU_APB1F_TMR6_STS_MASK       ((uint32)0x00000010U)
#define DBGMCU_APB1F_TMR6_STS_SHIFT      ((uint8)4U)

#define DBGMCU_APB1F_TMR4_STS_MASK       ((uint32)0x00000100U)
#define DBGMCU_APB1F_TMR4_STS_SHIFT      ((uint8)8U)

#define DBGMCU_APB1F_RTC_STS_MASK        ((uint32)0x00000400U)
#define DBGMCU_APB1F_RTC_STS_SHIFT       ((uint8)10U)

#define DBGMCU_APB1F_IWDT_STS_MASK       ((uint32)0x00001000U)
#define DBGMCU_APB1F_IWDT_STS_SHIFT      ((uint8)12U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: DBGMCU_APB2F (Base + 0x0C)
************************************************************************************************************/
/** DBGMCU_APB2F register address */
#define DBGMCU_APB2F_REG_ADDR            ((uint32)(DBGMCU_BASEADDR + (uint32)0x0CU))

#define DBGMCU_APB2F_TMR1_STS_MASK       ((uint32)0x00000800U)
#define DBGMCU_APB2F_TMR1_STS_SHIFT      ((uint8)11U)

#define DBGMCU_APB2F_TMR7_STS_MASK       ((uint32)0x00010000U)
#define DBGMCU_APB2F_TMR7_STS_SHIFT      ((uint8)16U)

#define DBGMCU_APB2F_TMR8_STS_MASK       ((uint32)0x00020000U)
#define DBGMCU_APB2F_TMR8_STS_SHIFT      ((uint8)17U)

/**@} end of group MCU_Macros */

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* MCU_DBGMCU_REG_H */

/**@} end of group MCU_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
