/*!
* @file     Can_Irq.c
*
* @version  1.0.0
*
* @brief    AUTOSAR CAN Driver interrupt routines
 *           
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_15-Nov-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifdef __cplusplus
extern "C"{
#endif

#include "Can.h"
#include "CanIf_Cbk.h"
#include "Mcal.h"
/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup CAN_Driver
  * @brief CAN driver modules
  @{
*/

/** @defgroup CAN_Macros
  @{
*/
/*******************************************************************************
                    VENDOR ID & AUTOSAR VERSION INFO
*******************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define CAN_IRQ_VENDOR_ID                       0x00C1U
/** Module ID of this module, as defined in the BSW Module List. */
#define CAN_IRQ_MODULE_ID                       0x0050U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */
#define CAN_IRQ_AR_RELEASE_MAJOR_VERSION        0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define CAN_IRQ_AR_RELEASE_MINOR_VERSION        0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define CAN_IRQ_AR_RELEASE_REVISION_VERSION     0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define CAN_IRQ_SW_MAJOR_VERSION                0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define CAN_IRQ_SW_MINOR_VERSION                0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define CAN_IRQ_SW_PATCH_VERSION                0x00U
/**@} end of group CAN_Macros */
/*******************************************************************************
                                VERSION CHECK
*******************************************************************************/
/* Make sure the vendor id is the same between Can_Irq.c and Can.h */
#if (CAN_IRQ_VENDOR_ID != CAN_H_VENDOR_ID)
    #error "Vendor id mismatch between Can_Irq.c and Can.h"
#endif
/* Make sure the module id is the same between Can_Irq.c and Can.h */
#if (CAN_IRQ_MODULE_ID != CAN_H_MODULE_ID)
    #error "Module id mismatch between Can_Irq.c and Can.h"
#endif
/* Make sure the AUTOSAR major version number is the same between Can_Irq.c and Can.h */
#if (CAN_IRQ_AR_RELEASE_MAJOR_VERSION != CAN_H_AR_RELEASE_MAJOR_VERSION)
    #error "AUTOSAR major version number mismatch between Can_Irq.c and Can.h"
#endif
/* Make sure the AUTOSAR minor version number is the same between Can_Irq.c and Can.h */
#if (CAN_IRQ_AR_RELEASE_MINOR_VERSION != CAN_H_AR_RELEASE_MINOR_VERSION)
    #error "AUTOSAR minor version number mismatch between Can_Irq.c and Can.h"
#endif
/* Make sure the AUTOSAR revision version number is the same between Can_Irq.c and Can.h */
#if (CAN_IRQ_AR_RELEASE_REVISION_VERSION != CAN_H_AR_RELEASE_REVISION_VERSION)
    #error "AUTOSAR revision version number mismatch between Can_Irq.c and Can.h"
#endif
/* Make sure the software major version number is the same between Can_Irq.c and Can.h */
#if (CAN_IRQ_SW_MAJOR_VERSION != CAN_H_SW_MAJOR_VERSION)
    #error "Software major version number mismatch between Can_Irq.c and Can.h"
#endif
/* Make sure the software minor version number is the same between Can_Irq.c and Can.h */
#if (CAN_IRQ_SW_MINOR_VERSION != CAN_H_SW_MINOR_VERSION)
    #error "Software minor version number mismatch between Can_Irq.c and Can.h"
#endif
/* Make sure the software patch version number is the same between Can_Irq.c and Can.h */
#if (CAN_IRQ_SW_PATCH_VERSION != CAN_H_SW_PATCH_VERSION)
    #error "Software patch version number mismatch between Can_Irq.c and Can.h"
#endif

#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Can_Irq.c and CanIf_Cbk.h */
    #if (CAN_IRQ_AR_RELEASE_MAJOR_VERSION != CANIF_CBK_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR major version number mismatch between Can_Irq.c and CanIf_Cbk.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Can_Irq.c and CanIf_Cbk.h */
    #if (CAN_IRQ_AR_RELEASE_MINOR_VERSION != CANIF_CBK_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR minor version number mismatch between Can_Irq.c and CanIf_Cbk.h"
    #endif
    /* Make sure the AUTOSAR major version number is the same between Can_Irq.c and Mcal.h */
    #if (CAN_IRQ_AR_RELEASE_MAJOR_VERSION != MCAL_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR major version number mismatch between Can_Irq.c and Mcal.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Can_Irq.c and Mcal.h */
    #if (CAN_IRQ_AR_RELEASE_MINOR_VERSION != MCAL_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR minor version number mismatch between Can_Irq.c and Mcal.h"
    #endif
#endif /* ENABLE_INTERMODULE_MCAL_CHECK */

/*******************************************************************************
                            LOCAL FUNCTIONS
*******************************************************************************/
/** @defgroup CAN_Fuctions
  @{
*/
#define CAN_START_SEC_CODE
#include "Can_MemMap.h"

FUNC(void, CAN_CODE) FDCAN_IT0_IRQHandler(void);
FUNC(void, CAN_CODE) FDCAN_IT1_IRQHandler(void);
FUNC(void, CAN_CODE) FDCAN_SERM_IRQHandler(void);

#if (STD_ON == CAN_BUSOFF_INTERRUPT_HANDLE_ENABLE)
/*!
* @brief    Handle BusOff condition.
*
* @param[in]    ControllerIndex        Index of the CAN controller
* @param[in]    ControllerOffset       Offset of the CAN controller
*/
static void Can_Irq_BusOffHandler(CONST(uint8, AUTOMATIC) ControllerIndex,
    CONST(uint8, AUTOMATIC) ControllerOffset)
{
    VAR(uint32, AUTOMATIC) tempInitStatus = 0U;
    
    /* Read Controller mode status:CCCR.B.INIT */
    tempInitStatus = REG_BIT_GET32(CAN_CCCR_REG_ADDR(ControllerOffset), CAN_CCCR_INIT_MASK);
    /* Check is in BusOff state or not */
    if((CAN_PSR_BO_MASK == REG_BIT_GET32(CAN_PSR_REG_ADDR(ControllerOffset), CAN_PSR_BO_MASK)) && \
        (CAN_CCCR_INIT_MASK == tempInitStatus) && (CAN_CS_STARTED == g_canControllerStatus[ControllerIndex].controllerState))
    {
        /* Invoke function to cancel all pending request */
        Can_Hw_CancelPendingTx(ControllerIndex);
        
        /* Set controller mode with STOP state */
        g_canControllerStatus[ControllerIndex].controllerState = CAN_CS_STOPPED;
        
        /* Call Bus_Off notification function to notify upper layer */
        CanIf_ControllerBusOff(ControllerIndex);
    }
    else
    {
        /* nothing */
    }
}

/*!
* @brief    Process bus off interrupt.
*
* @param[in]    ControllerIndex        Index of the CAN controller
* @param[in]    ControllerOffset       Offset of the CAN controller
*/
static FUNC(void, CAN_CODE) Can_Irq_ProcessBusOffInterrupt(CONST(uint8, AUTOMATIC) ControllerIndex,
    CONST(uint8, AUTOMATIC) ControllerOffset)
{
    /* Check if BusOff status is set */
    if(CAN_IR_BO_MASK == REG_BIT_GET32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_BO_MASK))
    {
    #if (STD_ON == CAN_PUBLIC_ICOM_ENABLE)
        if(((boolean)TRUE != g_canControllerStatus[ControllerIndex].icomEnableStatus) || \
            ((boolean)FALSE != g_canControllerStatus[ControllerIndex].icomConfgBOStatus))
        {
            /* If current state is STARTED,Invoke BusOff handler function */
            Can_Irq_BusOffHandler(ControllerIndex, ControllerOffset);
        }
        else
        {
            /* Intentionally Empty */
        }
    #else
        /* If current state is STARTED Invoke BusOff handler function */
        Can_Irq_BusOffHandler(ControllerIndex, ControllerOffset);
    #endif
    
        /* Clear BO flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_BO_MASK);
    }
    else
    {
        /* Intentionally Empty */
    }
}
#endif /* CAN_BUSOFF_INTERRUPT_HANDLE_ENABLE = STD_ON */

#if (STD_ON == CAN_RX_INTERRUPT_HANDLE_ENABLE)
/*!
* @brief    Process Dedicated Rx Buffer interrupt.
*
* @param[in]    ControllerIndex        Index of the CAN controller
* @param[in]    ControllerOffset       Offset of the CAN controller
*/
static FUNC(void, CAN_CODE) Can_Irq_ProcessDedBufRxInterrupt(CONST(uint8, AUTOMATIC) ControllerIndex,
    CONST(uint8, AUTOMATIC) ControllerOffset)
{
    VAR(uint8, AUTOMATIC) circleCnt = 0;

    /* Check if any of the Message stored to Dedicated Rx Buffer */
    while((CAN_IR_DRX_MASK == REG_BIT_GET32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_DRX_MASK)) && \
          (circleCnt < CAN_FLAG_IRQ_CHECK_COUNT))
    {
        /* Clear the DRX flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_DRX_MASK);
        circleCnt++;
    }
    
    /* If current state is START Invoke receive handler function */
    if((CAN_CS_STARTED == g_canControllerStatus[ControllerIndex].controllerState) && 
       (0U != g_canConfigPtr->rxMbConfigContainerPtr->rxMbCount))
    {
        /* Call receive handler with buffer type as dedicated */
        Can_Hw_ReceiveHandler(ControllerIndex, CAN_RX_DATA_CHECK_DEDICATED_BUFFER, FALSE, 0U);
    }
    else
    {
        /* Intentionally Empty */
    }
}

/*!
* @brief    Process Dedicated Rx Fifo interrupt.
*
* @param[in]    ControllerIndex        Index of the CAN controller
* @param[in]    ControllerOffset       Offset of the CAN controller
* @param[in]    RxFifoIndex            Index of the Rx Fifo
* @param[in]    RxFifoIntType          Type of Rx Fifo interrupt
*/
static FUNC(void, CAN_CODE) Can_Irq_ProcessFifoRxInterrupt(CONST(uint8, AUTOMATIC) ControllerIndex,
    CONST(uint8, AUTOMATIC) ControllerOffset, CONST(Can_RxFifoIndexType, AUTOMATIC) RxFifoIndex, 
    CONST(Can_RxFifoIntType, AUTOMATIC) RxFifoIntType)
{
    if(CAN_RX_FIFO0 == RxFifoIndex)
    {
        switch(RxFifoIntType)
        {
            case CAN_RX_FIFO_NEW_MESSAGE_INT:
                /* Clear RF0N flag */
                REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_RF0N_MASK);
                break;
            case CAN_RX_FIFO_WATERMARK_INT:
                /* Clear RF0W flag */
                REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_RF0W_MASK);
                break;
            case CAN_RX_FIFO_FULL_INT:
                /* Clear RF0F flag */
                REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_RF0F_MASK);
                break;
            default:
                /* Intentionally Empty */
                break;
        }
        
        /* If current state is STARTED Invoke receive handler function */
        if((CAN_CS_STARTED == g_canControllerStatus[ControllerIndex].controllerState) && 
           (0U != g_canConfigPtr->rxMbConfigContainerPtr->rxMbCount))
        {
            /* Call receive handler with buffer type as RXFIFO0 */
            Can_Hw_ReceiveHandler(ControllerIndex, CAN_RX_DATA_CHECK_FIFO0, FALSE, 0U);
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* Intentionally Empty */
    }

    if(CAN_RX_FIFO1 == RxFifoIndex)
    {
        switch(RxFifoIntType)
        {
            case CAN_RX_FIFO_NEW_MESSAGE_INT:
                /* Clear RF1N flag */
                REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_RF1N_MASK);
                break;
            case CAN_RX_FIFO_WATERMARK_INT:
                /* Clear RF1W flag */
                REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_RF1W_MASK);
                break;
            case CAN_RX_FIFO_FULL_INT:
                /* Clear RF1F flag */
                REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_RF1F_MASK);
                break;
            default:
                /* Intentionally Empty */
                break;
        }

        /* If current state is STARTED Invoke receive handler function */
        if((CAN_CS_STARTED == g_canControllerStatus[ControllerIndex].controllerState) && 
           (0U != g_canConfigPtr->rxMbConfigContainerPtr->rxMbCount))
        {
            /* Call receive handler with buffer type as RXFIFO1 */
            Can_Hw_ReceiveHandler(ControllerIndex, CAN_RX_DATA_CHECK_FIFO1, FALSE, 0U);
        }
        else
        {
            /* Intentionally Empty */
        }
    }
    else
    {
        /* Intentionally Empty */
    }
}
#endif /* STD_ON == CAN_RX_INTERRUPT_ENABLE */

#if (STD_ON == CAN_TX_INTERRUPT_HANDLE_ENABLE)
/*!
* @brief    Process Tx interrupt.
*
* @param[in]    ControllerIndex        Index of the CAN controller
* @param[in]    ControllerOffset       Offset of the CAN controller
* @param[in]    TxEvtIntType           Type of Tx Event interrupt
*/
static FUNC(void, CAN_CODE) Can_Irq_ProcessTxInterrupt(CONST(uint8, AUTOMATIC) ControllerIndex,
    CONST(uint8, AUTOMATIC) ControllerOffset, CONST(Can_TxEvtFifoIntType, AUTOMATIC) TxEvtIntType)
{
    switch(TxEvtIntType)
    {
        case CAN_TX_EVT_FIFO_NEW_ELE_INT:
            /* Clear TEFN flag */
            REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_TEFN_MASK);
            break;
        case CAN_TX_EVT_FIFO_WM_INT:
            /* Clear TEFW flag */
            REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_TEFW_MASK);
            break;
        case CAN_TX_EVT_FIFO_FULL_INT:
            /* Clear TEFF flag */
            REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_TEFF_MASK);
            break;
        default:
            /* Intentionally Empty */
            break;
    }
    
    /* If Config Pointer is not NULL */
    if((0U != g_canConfigPtr->txMbConfigContainerPtr->txMbCount) &&
       (CAN_CS_STARTED == g_canControllerStatus[ControllerIndex].controllerState))
    {
        /* If New Event Entry is present then invoke Tx handler */
        Can_Hw_TxEventHandler(ControllerIndex);
    }
    else
    {
        /* nothing */
    }
}
#endif

/*!
* @brief     Process CAN interrupt.
*
* @param[in]    ControllerIndex        Index of the CAN controller
* @param[in]    ControllerOffset       Offset of the CAN controller
* @param[in]    IntLine                Interrupt line
*/
static FUNC(void, CAN_CODE) Can_Irq_ProcessInterrupt(CONST(uint8, AUTOMATIC) ControllerIndex,
    CONST(uint8, AUTOMATIC) ControllerOffset, CONST(Can_InterruptLineType, AUTOMATIC) IntLine)
{
    VAR(uint32, AUTOMATIC) ilsRegVal = 0U;
    VAR(uint32, AUTOMATIC) irRegVal = 0U;
    VAR(uint32, AUTOMATIC) ieRegVal = 0U;
    P2CONST(Can_NotificationConfigType, AUTOMATIC, CAN_CONST) notificationConfigPtr = 
        g_canConfigPtr->controllersInfoPtr[ControllerIndex].notificationConfigPtr;
    
    /* Read Interrupt Line Select Register */
    ilsRegVal = REG_READ32(CAN_ILS_REG_ADDR(ControllerOffset));
    
    /* Read Interrupt Register */
    irRegVal = REG_READ32(CAN_IR_REG_ADDR(ControllerOffset));

    /* Read Interrupt Enable Register */
    ieRegVal = REG_READ32(CAN_IE_REG_ADDR(ControllerOffset));

#if (STD_ON == CAN_RXFIFO_ENABLE)
#if (STD_ON == CAN_RX_INTERRUPT_HANDLE_ENABLE)
    /* RF0NL:Rx Fifo 0 new message interrupt */
    if(((uint32)IntLine == (ilsRegVal & CAN_ILS_RF0NL_MASK)) &&
       (CAN_IR_RF0N_MASK == (irRegVal & CAN_IR_RF0N_MASK)) && 
       (CAN_IE_RF0NE_MASK == (ieRegVal & CAN_IE_RF0NE_MASK)))
    {
        Can_Irq_ProcessFifoRxInterrupt(ControllerIndex, ControllerOffset, CAN_RX_FIFO0, CAN_RX_FIFO_NEW_MESSAGE_INT);
    }
    else
    {
        /* nothing */
    }

    /* RF0WL:Rx Fifo 0 watermark interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_RF0WL_MASK) >> CAN_ILS_RF0WL_SHIFT)) &&
       (CAN_IR_RF0W_MASK == (irRegVal & CAN_IR_RF0W_MASK)) &&
       (CAN_IE_RF0WE_MASK == (ieRegVal & CAN_IE_RF0WE_MASK)))
    {
        Can_Irq_ProcessFifoRxInterrupt(ControllerIndex, ControllerOffset, CAN_RX_FIFO0, CAN_RX_FIFO_WATERMARK_INT);
    }
    else
    {
        /* nothing */
    }

    /* RF0FL:Rx Fifo 0 full interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_RF0FL_MASK) >> CAN_ILS_RF0FL_SHIFT)) &&
       (CAN_IR_RF0F_MASK == (irRegVal & CAN_IR_RF0F_MASK))
       && (CAN_IE_RF0FE_MASK == (ieRegVal & CAN_IE_RF0FE_MASK)))
    {
        Can_Irq_ProcessFifoRxInterrupt(ControllerIndex, ControllerOffset, CAN_RX_FIFO0, CAN_RX_FIFO_FULL_INT);
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_RX_INTERRUPT_HANDLE_ENABLE */

#if (STD_ON == CAN_RXFIFO_MSG_LOST_NOTIFICATION_ENABLE)
    /* RF0LL:Rx Fifo 0 message lost interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_RF0LL_MASK) >> CAN_ILS_RF0LL_SHIFT)) &&
       (CAN_IR_RF0L_MASK == (irRegVal & CAN_IR_RF0L_MASK)) && 
       (CAN_IE_RF0LE_MASK == (ieRegVal & CAN_IE_RF0LE_MASK)))
    {
        /* Clear RF0 flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_RF0L_MASK);
        if(NULL_PTR != notificationConfigPtr->rxFifo0LostMsgNotification)
        {
            notificationConfigPtr->rxFifo0LostMsgNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_RXFIFO_MSG_LOST_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_RX_INTERRUPT_HANDLE_ENABLE)
    /* RF1NL: Rx Fifo 1 new message interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_RF1NL_MASK) >> CAN_ILS_RF1NL_SHIFT)) &&
       (CAN_IR_RF1N_MASK == (irRegVal & CAN_IR_RF1N_MASK)) && 
       (CAN_IE_RF1NE_MASK == (ieRegVal & CAN_IE_RF1NE_MASK)))
    {
        Can_Irq_ProcessFifoRxInterrupt(ControllerIndex, ControllerOffset, CAN_RX_FIFO1, CAN_RX_FIFO_NEW_MESSAGE_INT);
    }
    else
    {
        /* nothing */
    }

    /* RF1WL: Rx Fifo 1 watermark interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_RF1WL_MASK) >> CAN_ILS_RF1WL_SHIFT)) &&
       (CAN_IR_RF1W_MASK == (irRegVal & CAN_IR_RF1W_MASK)) && 
       (CAN_IE_RF1WE_MASK == (ieRegVal & CAN_IE_RF1WE_MASK)))
    {
        Can_Irq_ProcessFifoRxInterrupt(ControllerIndex, ControllerOffset, CAN_RX_FIFO1, CAN_RX_FIFO_WATERMARK_INT);
    }
    else
    {
        /* nothing */
    }

    /* RF1FL: Rx Fifo 1 full interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_RF1FL_MASK) >> CAN_ILS_RF1FL_SHIFT)) &&
       (CAN_IR_RF1F_MASK == (irRegVal & CAN_IR_RF1F_MASK)) &&
       (CAN_IE_RF1FE_MASK == (ieRegVal & CAN_IE_RF1FE_MASK)))
    {
        Can_Irq_ProcessFifoRxInterrupt(ControllerIndex, ControllerOffset, CAN_RX_FIFO1, CAN_RX_FIFO_FULL_INT);
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_RX_INTERRUPT_HANDLE_ENABLE */

#if (STD_ON == CAN_RXFIFO_MSG_LOST_NOTIFICATION_ENABLE)
    /* RF1LL: Rx Fifo 1 message lost interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_RF1LL_MASK) >> CAN_ILS_RF1LL_SHIFT)) &&
       (CAN_IR_RF1L_MASK == (irRegVal & CAN_IR_RF1L_MASK)) &&
       (CAN_IE_RF1LE_MASK == (ieRegVal & CAN_IE_RF1LE_MASK)))
    {
        /* Clear RF1 flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_RF1L_MASK);
        if(NULL_PTR != notificationConfigPtr->rxFifo1LostMsgNotification)
        {
            notificationConfigPtr->rxFifo1LostMsgNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_RXFIFO_MSG_LOST_NOTIFICATION_ENABLE */
#endif /* STD_ON == CAN_RXFIFO_ENABLE */

#if (STD_ON == CAN_HIGH_PRIORITY_MSG_NOTIFICATION_ENABLE)
    /* HPML: High priority message interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_HPML_MASK) >> CAN_ILS_HPML_SHIFT)) &&
       (CAN_IR_HPM_MASK == (irRegVal & CAN_IR_HPM_MASK)) && 
       (CAN_IE_HPME_MASK == (ieRegVal & CAN_IE_HPME_MASK)))
    {
        /* Clear HPM flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_HPM_MASK);
        if(NULL_PTR != notificationConfigPtr->highPriorityMsgNotification)
        {
            notificationConfigPtr->highPriorityMsgNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_HIGH_PRIORITY_MSG_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_TRANS_COMPLETE_NOTIFICATION_ENABLE)
    /* TCL: Transmission completed interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_TCL_MASK) >> CAN_ILS_TCL_SHIFT)) &&
       (CAN_IR_TC_MASK == (irRegVal & CAN_IR_TC_MASK)) && 
       (CAN_IE_TCE_MASK == (ieRegVal & CAN_IE_TCE_MASK)))
    {
        /* Clear TC flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_TC_MASK);
        if(NULL_PTR != notificationConfigPtr->txCompleteNotification)
        {
            notificationConfigPtr->txCompleteNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_TRANS_COMPLETE_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_CANCEL_FINISHED_NOTIFICATION_ENABLE)
    /* TCFL: Transmission cancellation finished interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_TCFL_MASK) >> CAN_ILS_TCFL_SHIFT)) &&
       (CAN_IR_TCF_MASK == (irRegVal & CAN_IR_TCF_MASK)) && 
       (CAN_IE_TCFE_MASK == (ieRegVal & CAN_IE_TCFE_MASK)))
    {
        /* Clear TCF flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_TCF_MASK);
        if(NULL_PTR != notificationConfigPtr->txCancelFinishedNotification)
        {
            notificationConfigPtr->txCancelFinishedNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_CANCEL_FINISHED_NOTIFICATION_ENABLE */

#if (STD_ON == CNA_TX_FIFO_EMPTY_NOTIFICATION_ENABLE)
    /* TFEL: Tx FIFO empty interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_TFEL_MASK) >> CAN_ILS_TFEL_SHIFT)) &&
       (CAN_IR_TFE_MASK == (irRegVal & CAN_IR_TFE_MASK)) && 
       (CAN_IE_TFEE_MASK == (ieRegVal & CAN_IE_TFEE_MASK)))
    {
        /* Clear TFE flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_TFE_MASK);
        if(NULL_PTR != notificationConfigPtr->txFifoEmptyNotification)
        {
            notificationConfigPtr->txFifoEmptyNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CNA_TX_FIFO_EMPTY_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_TX_INTERRUPT_HANDLE_ENABLE)
    /* TEFNL: Tx Event FIFO new element interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_TEFNL_MASK) >> CAN_ILS_TEFNL_SHIFT)) &&
       (CAN_IR_TEFN_MASK == (irRegVal & CAN_IR_TEFN_MASK)) && 
       (CAN_IE_TEFNE_MASK == (ieRegVal & CAN_IE_TEFNE_MASK)))
    {
        Can_Irq_ProcessTxInterrupt(ControllerIndex, ControllerOffset, CAN_TX_EVT_FIFO_NEW_ELE_INT);
    }
    else
    {
        /* nothing */
    }

    /* TEFWL: Tx Event FIFO watermark interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_TEFWL_MASK) >> CAN_ILS_TEFWL_SHIFT)) &&
       (CAN_IR_TEFW_MASK == (irRegVal & CAN_IR_TEFW_MASK)) && 
       (CAN_IE_TEFWE_MASK == (ieRegVal & CAN_IE_TEFWE_MASK)))
    {
        Can_Irq_ProcessTxInterrupt(ControllerIndex, ControllerOffset, CAN_TX_EVT_FIFO_WM_INT);
    }
    else
    {
        /* nothing */
    }

    /* TEFFL: Tx Event FIFO full interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_TEFFL_MASK) >> CAN_ILS_TEFFL_SHIFT)) &&
       (CAN_IR_TEFF_MASK == (irRegVal & CAN_IR_TEFF_MASK)) && 
       (CAN_IE_TEFFE_MASK == (ieRegVal & CAN_IE_TEFFE_MASK)))
    {
        Can_Irq_ProcessTxInterrupt(ControllerIndex, ControllerOffset, CAN_TX_EVT_FIFO_FULL_INT);
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_TX_INTERRUPT_HANDLE_ENABLE */

#if (STD_ON == CAN_TX_EVT_FIFO_LOST_ELE_NOTIFICATION_ENABLE)
    /* TEFLL: Tx Event FIFO element lost interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_TEFLL_MASK) >> CAN_ILS_TEFLL_SHIFT)) &&
       (CAN_IR_TEFL_MASK == (irRegVal & CAN_IR_TEFL_MASK)) && 
       (CAN_IE_TEFLE_MASK == (ieRegVal & CAN_IE_TEFLE_MASK)))
    {
        /* Clear TEF flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_TEFL_MASK);
        if(NULL_PTR != notificationConfigPtr->txEvtFifoLostMsgNotification)
        {
            notificationConfigPtr->txEvtFifoLostMsgNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_TX_EVT_FIFO_LOST_ELE_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_TIMESTAMP_OVERFLOW_NOTIFICATION_ENABLE)
    /* TSWL: Timestamp wraparound interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_TSWL_MASK) >> CAN_ILS_TSWL_SHIFT)) &&
       (CAN_IR_TSW_MASK == (irRegVal & CAN_IR_TSW_MASK)) && 
       (CAN_IE_TSWE_MASK == (ieRegVal & CAN_IE_TSWE_MASK)))
    {
        /* Clear TSW flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_TSW_MASK);
        if(NULL_PTR != notificationConfigPtr->timeStampOverFlowNotification)
        {
            notificationConfigPtr->timeStampOverFlowNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_TIMESTAMP_OVERFLOW_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_RAM_ACC_FAILED_NOTIFICATION_ENABLE)
    /* MRAFL: Message RAM access failure interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_MRAFL_MASK) >> CAN_ILS_MRAFL_SHIFT)) &&
       (CAN_IR_MRAF_MASK == (irRegVal & CAN_IR_MRAF_MASK)) && 
       (CAN_IE_MRAFE_MASK == (ieRegVal & CAN_IE_MRAFE_MASK)))
    {
        /* Clear MRAF flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_MRAF_MASK);
        if(NULL_PTR != notificationConfigPtr->msgRamAccessFailureNotification)
        {
            notificationConfigPtr->msgRamAccessFailureNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_RAM_ACC_FAILED_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_TIME_OVERFLOW_NOTIFICATION_ENABLE)
    /* TOOL: Time Overflow interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_TOOL_MASK) >> CAN_ILS_TOOL_SHIFT)) &&
       (CAN_IR_TOO_MASK == (irRegVal & CAN_IR_TOO_MASK)) && 
       (CAN_IE_TOOE_MASK == (ieRegVal & CAN_IE_TOOE_MASK)))
    {
        /* Clear TOO flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_TOO_MASK);
        if(NULL_PTR != notificationConfigPtr->timeOverFlowNotification)
        {
            notificationConfigPtr->timeOverFlowNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_TIME_OVERFLOW_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_RX_INTERRUPT_HANDLE_ENABLE)
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_DRXL_MASK) >> CAN_ILS_DRXL_SHIFT)) &&
       (CAN_IR_DRX_MASK == (irRegVal & CAN_IR_DRX_MASK)) && 
       (CAN_IE_DRXE_MASK == (ieRegVal & CAN_IE_DRXE_MASK)))
    {
        Can_Irq_ProcessDedBufRxInterrupt(ControllerIndex, ControllerOffset);
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_RX_INTERRUPT_HANDLE_ENABLE */

#if (STD_ON == CAN_ERROR_LOG_OVERFLOW_NOTIFICATION_ENABLE)
    /* ELOL: Error logging overflow interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_ELOL_MASK) >> CAN_ILS_ELOL_SHIFT)) &&
       (CAN_IR_ELO_MASK == (irRegVal & CAN_IR_ELO_MASK)) && 
       (CAN_IE_ELOE_MASK == (ieRegVal & CAN_IE_ELOE_MASK)))
    {
        /* Clear ELO flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_ELO_MASK);
        if(NULL_PTR != notificationConfigPtr->errorLogOverFlowNotification)
        {
            notificationConfigPtr->errorLogOverFlowNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_ERROR_LOG_OVERFLOW_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_ERROR_PASSIVE_NOTIFICATION_ENABLE)
    /* EPL: Error Passive Level interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_EPL_MASK) >> CAN_ILS_EPL_SHIFT)) &&
       (CAN_IR_EP_MASK == (irRegVal & CAN_IR_EP_MASK)) && 
       (CAN_IE_EPE_MASK == (ieRegVal & CAN_IE_EPE_MASK)))
    {
        /* Clear EP flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_EP_MASK);
        if(NULL_PTR != notificationConfigPtr->errorPassiveNotification)
        {
            notificationConfigPtr->errorPassiveNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_ERROR_PASSIVE_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_ERROR_WARNING_NOTIFICATION_ENABLE)
    /* EWL: Error Warning Level interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_EWL_MASK) >> CAN_ILS_EWL_SHIFT)) &&
       (CAN_IR_EW_MASK == (irRegVal & CAN_IR_EW_MASK)) && 
       (CAN_IE_EWE_MASK == (ieRegVal & CAN_IE_EWE_MASK)))
    {
        /* Clear EW flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_EW_MASK);
        if(NULL_PTR != notificationConfigPtr->errorWarningNotification)
        {
            notificationConfigPtr->errorWarningNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_ERROR_WARNING_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_BUSOFF_INTERRUPT_HANDLE_ENABLE)
    /* BOL: Bus Off interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_BOL_MASK) >> CAN_ILS_BOL_SHIFT)) &&
       (CAN_IR_BO_MASK == (irRegVal & CAN_IR_BO_MASK)) && 
       (CAN_IE_BOE_MASK == (ieRegVal & CAN_IE_BOE_MASK)))
    {
        Can_Irq_ProcessBusOffInterrupt(ControllerIndex, ControllerOffset);
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_BUSOFF_INTERRUPT_HANDLE_ENABLE */

#if (STD_ON == CAN_WDG_NOTIFICATION_ENABLE)
    /* WDI: Watchdog interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_WDIL_MASK) >> CAN_ILS_WDIL_SHIFT)) &&
       (CAN_IR_WDI_MASK == (irRegVal & CAN_IR_WDI_MASK)) && 
       (CAN_IE_WDIE_MASK == (ieRegVal & CAN_IE_WDIE_MASK)))
    {
        /* Clear WDI flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_WDI_MASK);
        if(NULL_PTR != notificationConfigPtr->watchdogNotification)
        {
            notificationConfigPtr->watchdogNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_WDG_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_PLROTOCOL_ERROR_ARB_NOTIFICATION_ENABLE)
    /* PEAL: Protocol Error in Arbitration Phase interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_PEAL_MASK) >> CAN_ILS_PEAL_SHIFT)) &&
       (CAN_IR_PEA_MASK == (irRegVal & CAN_IR_PEA_MASK)) &&
       (CAN_IE_PEAE_MASK == (ieRegVal & CAN_IE_PEAE_MASK)))
    {
        /* Clear PEA flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_PEA_MASK);
        if(NULL_PTR != notificationConfigPtr->protocolErrorArbNotification)
        {
            notificationConfigPtr->protocolErrorArbNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_PLROTOCOL_ERROR_ARB_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_PLROTOCOL_ERROR_DATA_NOTIFICATION_ENABLE)
    /* PEDL: Protocol Error in Data Phase interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_PEDL_MASK) >> CAN_ILS_PEDL_SHIFT)) &&
       (CAN_IR_PED_MASK == (irRegVal & CAN_IR_PED_MASK)) && 
       (CAN_IE_PEDE_MASK == (ieRegVal & CAN_IE_PEDE_MASK)))
    {
        /* Clear PED flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_PED_MASK);
        if(NULL_PTR != notificationConfigPtr->protocolErrorDataNotification)
        {
            notificationConfigPtr->protocolErrorDataNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_PLROTOCOL_ERROR_DATA_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_ACC_RESERVED_ADDR_NOTIFICATION_ENABLE)
    /* ARAL: Access to Reserved Address interrupt */
    if(((uint32)IntLine == ((ilsRegVal & CAN_ILS_ARAL_MASK) >> CAN_ILS_ARAL_SHIFT)) &&
       (CAN_IR_ARA_MASK == (irRegVal & CAN_IR_ARA_MASK)) && 
       (CAN_IE_ARAE_MASK == (ieRegVal & CAN_IE_ARAE_MASK)))
    {
        /* Clear ARA flag */
        REG_WRITE32(CAN_IR_REG_ADDR(ControllerOffset), CAN_IR_ARA_MASK);
        if(NULL_PTR != notificationConfigPtr->accessReservedAddrNotification)
        {
            notificationConfigPtr->accessReservedAddrNotification();
        }
        else
        {
            /* nothing */
        }
    }
    else
    {
        /* nothing */
    }
#endif /* STD_ON == CAN_ACC_RESERVED_ADDR_NOTIFICATION_ENABLE */
}

#if (STD_ON == CAN_WAKEUP_NOTIFICATION_ENABLE)
/*!
* @brief      Process Wakeup interrupt.
*/
static FUNC(void, CAN_CODE) Can_Irq_ProcessWakeupInterrupt(CONST(uint8, AUTOMATIC) ControllerIndex)
{
    VAR(uint32, AUTOMATIC) ctrlRegVal = 0U;
    VAR(uint32, AUTOMATIC) stsRegVal = 0U;
    P2CONST(Can_NotificationConfigType, AUTOMATIC, CAN_CONST) notificationConfigPtr = 
        g_canConfigPtr->controllersInfoPtr[ControllerIndex].notificationConfigPtr;

    /* Read Control Register */
    ctrlRegVal = REG_READ32(CAN_ERM_CTRL_REG_ADDR);
    stsRegVal = REG_READ32(CAN_ERM_STS_REG_ADDR);

    if((CAN_ERM_CTRL_WAKE_INT_EN_MASK == (ctrlRegVal & CAN_ERM_CTRL_WAKE_INT_EN_MASK)) && 
       (CAN_ERM_STS_CAN_WAKEUP_FLAG_MASK == (stsRegVal & CAN_ERM_STS_CAN_WAKEUP_FLAG_MASK)))
    {
        /* Clear Wakeup Flag */
        REG_BIT_SET32(CAN_ERM_STS_REG_ADDR, CAN_ERM_STS_CAN_WAKEUP_FLAG_MASK);

        if(NULL_PTR != notificationConfigPtr->wakeupNotification)
        {
            notificationConfigPtr->wakeupNotification();
        }
        else
        {
            /* Intentionally Empty */
        }
    }
    else
    {
        /* Intentionally Empty */
    }
}
#endif /* STD_ON == CAN_WAKEUP_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_ECC_ERROR_NOTIFICATION_ENABLE)
static FUNC(void, CAN_CODE) Can_Irq_ProcessEccInterrupt(CONST(uint8, AUTOMATIC) ControllerIndex)
{
#if (STD_ON == CAN_ECC_ERROR_UNCORRECT_NOTIFICATION_ENABLE) || (STD_ON == CAN_ECC_ERROR_CORRECT_NOTIFICATION_ENABLE)
    VAR(uint32, AUTOMATIC) ctrlRegVal = 0U;
    VAR(uint32, AUTOMATIC) stsRegVal = 0U;
    VAR(uint32, AUTOMATIC) logRegVal = 0U;

    P2CONST(Can_NotificationConfigType, AUTOMATIC, CAN_CONST) notificationConfigPtr = 
        g_canConfigPtr->controllersInfoPtr[ControllerIndex].notificationConfigPtr;

    /* Read ECC Control Register */
    ctrlRegVal = REG_READ32(CAN_ERM_CTRL_REG_ADDR);
    /* Read ECC Status Register */
    stsRegVal = REG_READ32(CAN_ERM_STS_REG_ADDR);
    /* Read ECC Log Register */
    logRegVal = REG_READ32(CAN_ERM_ECCLOG_REG_ADDR);
#endif /* STD_ON == CAN_ECC_ERROR_UNCORRECT_NOTIFICATION_ENABLE || STD_ON == CAN_ECC_ERROR_CORRECT_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_ECC_ERROR_CORRECT_NOTIFICATION_ENABLE)
    if((CAN_ERM_CTRL_BEC_INT_EN_MASK == (ctrlRegVal & CAN_ERM_CTRL_BEC_INT_EN_MASK)) && 
       (CAN_ERM_STS_BEC_FLAG_MASK == (stsRegVal & CAN_ERM_STS_BEC_FLAG_MASK)))
    {
        /* Clear BEC Flag */
        REG_BIT_SET32(CAN_ERM_STS_REG_ADDR, CAN_ERM_STS_BEC_FLAG_MASK);

        if(NULL_PTR != notificationConfigPtr->eccErrorCorrectNotification)
        {
            notificationConfigPtr->eccErrorCorrectNotification(logRegVal);
        }
        else
        {
            /* Intentionally Empty */
        }
    }
    else
    {
        /* Intentionally Empty */
    }
#endif /* STD_ON == CAN_ECC_ERROR_CORRECT_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_ECC_ERROR_UNCORRECT_NOTIFICATION_ENABLE)
    if((CAN_ERM_CTRL_BEU_INT_EN_MASK == (ctrlRegVal & CAN_ERM_CTRL_BEU_INT_EN_MASK)) && 
       (CAN_ERM_STS_BEU_FLAG_MASK == (stsRegVal & CAN_ERM_STS_BEU_FLAG_MASK)))
    {
        /* Clear UCE Flag */
        REG_BIT_SET32(CAN_ERM_STS_REG_ADDR, CAN_ERM_STS_BEU_FLAG_MASK);

        if(NULL_PTR != notificationConfigPtr->eccErrorUnCorrectNotification)
        {
            notificationConfigPtr->eccErrorUnCorrectNotification(logRegVal);
        }
        else
        {
            /* Intentionally Empty */
        }
    }
    else
    {
        /* Intentionally Empty */
    }
#endif /* STD_ON == CAN_ECC_ERROR_UNCORRECT_NOTIFICATION_ENABLE */
}
#endif /* STD_ON == CAN_ECC_ERROR_NOTIFICATION_ENABLE */
/*******************************************************************************
                            GLOBAL FUNCTIONS
*******************************************************************************/
FUNC(void, CAN_CODE) FDCAN_IT0_IRQHandler(void)
{
    Can_Irq_ProcessInterrupt(CAN_CONTROLLER_LOG_INDEX0, CAN_CAONTROLLER_HW_INDEX0, CAN_INTERRUPT_LINE0);
    EXIT_INTERRUPT();
}

FUNC(void, CAN_CODE) FDCAN_IT1_IRQHandler(void)
{
    Can_Irq_ProcessInterrupt(CAN_CONTROLLER_LOG_INDEX0, CAN_CAONTROLLER_HW_INDEX0, CAN_INTERRUPT_LINE1);
    EXIT_INTERRUPT();
}

FUNC(void, CAN_CODE) FDCAN_SERM_IRQHandler(void)
{
#if (STD_ON == CAN_WAKEUP_NOTIFICATION_ENABLE)
    Can_Irq_ProcessWakeupInterrupt(CAN_CONTROLLER_LOG_INDEX0);
#endif /* STD_ON == CAN_WAKEUP_NOTIFICATION_ENABLE */

#if (STD_ON == CAN_ECC_ERROR_NOTIFICATION_ENABLE)
    Can_Irq_ProcessEccInterrupt(CAN_CONTROLLER_LOG_INDEX0);
#endif

    EXIT_INTERRUPT();
}

#define CAN_STOP_SEC_CODE
#include "Can_MemMap.h"

/**@} end of group CAN_Fuctions */
#ifdef __cplusplus
}
#endif
/**@} end of group CAN_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
