/*!
* @file     Pwm_Tmr.c
*
* @version  1.0.0
*
* @brief    pwm driver code by TMR code
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifdef __cplusplus
extern "C" {
#endif

#include "modules.h"
#include "Pdl_TmrReg.h"
#include "Mcu_RcmTypes.h"
#include "Pwm_Tmr.h"
#include "Pwm_Notif.h"
#include "StdRegMacros.h"
#include "SchM_Pwm.h"
#include "Dio_Reg.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup PWM_Driver
  * @brief PWM driver modules
  @{
*/

/** @defgroup PWM_Macros
  @{
*/
/**************************************************************************
                  VENDOR ID & AUTOSAR VERSION INFO
**************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define PWM_TMR_VENDOR_ID                      0x00C1U
/** Module ID of this module, as defined in the BSW Module List. */
#define PWM_TMR_MODULE_ID                      0x0079U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PWM_TMR_AR_RELEASE_MAJOR_VERSION       0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PWM_TMR_AR_RELEASE_MINOR_VERSION       0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PWM_TMR_AR_RELEASE_REVISION_VERSION    0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PWM_TMR_SW_MAJOR_VERSION               0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PWM_TMR_SW_MINOR_VERSION               0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PWM_TMR_SW_PATCH_VERSION               0x00U

/**@} end of group PWM_Macros */

/**************************************************************************
                    VERSION INFOMATION VERIFICATION
**************************************************************************/
/* Make sure the AUTOSAR major version number is the same between Pwm_Tmr.c and modules.h */
#if (PWM_TMR_AR_RELEASE_MAJOR_VERSION != MODULE_H_AR_RELEASE_MAJOR_VERSION)
    #error "AUTOSAR Major Version Number mismatch between Pwm_Tmr.c and modules.h "
#endif
/* Make sure the AUTOSAR minor version number is the same between Pwm_Tmr.c and modules.h */
#if (PWM_TMR_AR_RELEASE_MINOR_VERSION != MODULE_H_AR_RELEASE_MINOR_VERSION)
    #error "AUTOSAR Minor Version Number mismatch between Pwm_Tmr.c and modules.h "
#endif

/* Make sure the vendor id is the same between Pwm_Tmr.c and Pdl_TmrReg.h */
#if (PWM_TMR_VENDOR_ID != PDL_TMR_REG_H_VENDOR_ID)
    #error "Vendor id mismatch between Pwm_Tmr.c and Pdl_TmrReg.h "
#endif
/* Make sure the AUTOSAR major version number is the same between Pwm_Tmr.c and Pdl_TmrReg.h */
#if (PWM_TMR_AR_RELEASE_MAJOR_VERSION != PDL_TMR_REG_H_AR_RELEASE_MAJOR_VERSION)
    #error "AUTOSAR Major Version Number mismatch between Pwm_Tmr.c and Pdl_TmrReg.h "
#endif
/* Make sure the AUTOSAR minor version number is the same between Pwm_Tmr.c and Pdl_TmrReg.h */
#if (PWM_TMR_AR_RELEASE_MINOR_VERSION != PDL_TMR_REG_H_AR_RELEASE_MINOR_VERSION)
    #error "AUTOSAR Minor Version Number mismatch between Pwm_Tmr.c and Pdl_TmrReg.h "
#endif
/* Make sure the AUTOSAR revision version number is the same between Pwm_Tmr.c and Pdl_TmrReg.h */
#if (PWM_TMR_AR_RELEASE_REVISION_VERSION != PDL_TMR_REG_H_AR_RELEASE_REVISION_VERSION)
    #error "AUTOSAR Revision Version Number mismatch between Pwm_Tmr.c and Pdl_TmrReg.h "
#endif
/* Make sure the software major version number is the same between Pwm_Tmr.c and Pdl_TmrReg.h */
#if (PWM_TMR_SW_MAJOR_VERSION != PDL_TMR_REG_H_SW_MAJOR_VERSION)
    #error "Software Major Version Number mismatch between Pwm_Tmr.c and Pdl_TmrReg.h "
#endif
/* Make sure the software minor version number is the same between Pwm_Tmr.c and Pdl_TmrReg.h */
#if (PWM_TMR_SW_MINOR_VERSION != PDL_TMR_REG_H_SW_MINOR_VERSION)
    #error "Software Minor Version Number mismatch between Pwm_Tmr.c and Pdl_TmrReg.h "
#endif
/* Make sure the software patch version number is the same between Pwm_Tmr.c and Pdl_TmrReg.h */
#if (PWM_TMR_SW_PATCH_VERSION != PDL_TMR_REG_H_SW_PATCH_VERSION)
    #error "Software Patch Version Number mismatch between Pwm_Tmr.c and Pdl_TmrReg.h "
#endif

/* Make sure the vendor id is the same between Pwm_Tmr.c and Mcu_RcmTypes.h */
#if (PWM_TMR_VENDOR_ID != MCU_RCM_TYPES_H_VENDOR_ID)
    #error "Vendor id mismatch between Pwm_Tmr.c and Mcu_RcmTypes.h "
#endif
/* Make sure the AUTOSAR major version number is the same between Pwm_Tmr.c and Mcu_RcmTypes.h */
#if (PWM_TMR_AR_RELEASE_MAJOR_VERSION != MCU_RCM_TYPES_H_AR_RELEASE_MAJOR_VERSION)
    #error "AUTOSAR Major Version Number mismatch between Pwm_Tmr.c and Mcu_RcmTypes.h "
#endif
/* Make sure the AUTOSAR minor version number is the same between Pwm_Tmr.c and Mcu_RcmTypes.h */
#if (PWM_TMR_AR_RELEASE_MINOR_VERSION != MCU_RCM_TYPES_H_AR_RELEASE_MINOR_VERSION)
    #error "AUTOSAR Minor Version Number mismatch between Pwm_Tmr.c and Mcu_RcmTypes.h "
#endif
/* Make sure the AUTOSAR revision version number is the same between Pwm_Tmr.c and Mcu_RcmTypes.h */
#if (PWM_TMR_AR_RELEASE_REVISION_VERSION != MCU_RCM_TYPES_H_AR_RELEASE_REVISION_VERSION)
    #error "AUTOSAR Revision Version Number mismatch between Pwm_Tmr.c and Mcu_RcmTypes.h "
#endif
/* Make sure the software major version number is the same between Pwm_Tmr.c and Mcu_RcmTypes.h */
#if (PWM_TMR_SW_MAJOR_VERSION != MCU_RCM_TYPES_H_SW_MAJOR_VERSION)
    #error "Software Major Version Number mismatch between Pwm_Tmr.c and Mcu_RcmTypes.h "
#endif
/* Make sure the software minor version number is the same between Pwm_Tmr.c and Mcu_RcmTypes.h */
#if (PWM_TMR_SW_MINOR_VERSION != MCU_RCM_TYPES_H_SW_MINOR_VERSION)
    #error "Software Minor Version Number mismatch between Pwm_Tmr.c and Mcu_RcmTypes.h "
#endif
/* Make sure the software patch version number is the same between Pwm_Tmr.c and Mcu_RcmTypes.h */
#if (PWM_TMR_SW_PATCH_VERSION != MCU_RCM_TYPES_H_SW_PATCH_VERSION)
    #error "Software Patch Version Number mismatch between Pwm_Tmr.c and Mcu_RcmTypes.h "
#endif

/* Make sure the vendor id is the same between Pwm_Tmr.c and Pwm_Tmr.h */
#if (PWM_TMR_VENDOR_ID != PWM_TMR_H_VENDOR_ID)
    #error "Vendor id mismatch between Pwm_Tmr.c and Pwm_Tmr.h "
#endif
/* Make sure the AUTOSAR major version number is the same between Pwm_Tmr.c and Pwm_Tmr.h */
#if (PWM_TMR_AR_RELEASE_MAJOR_VERSION != PWM_TMR_H_AR_RELEASE_MAJOR_VERSION)
    #error "AUTOSAR Major Version Number mismatch between Pwm_Tmr.c and Pwm_Tmr.h "
#endif
/* Make sure the AUTOSAR minor version number is the same between Pwm_Tmr.c and Pwm_Tmr.h */
#if (PWM_TMR_AR_RELEASE_MINOR_VERSION != PWM_TMR_H_AR_RELEASE_MINOR_VERSION)
    #error "AUTOSAR Minor Version Number mismatch between Pwm_Tmr.c and Pwm_Tmr.h "
#endif
/* Make sure the AUTOSAR revision version number is the same between Pwm_Tmr.c and Pwm_Tmr.h */
#if (PWM_TMR_AR_RELEASE_REVISION_VERSION != PWM_TMR_H_AR_RELEASE_REVISION_VERSION)
    #error "AUTOSAR Revision Version Number mismatch between Pwm_Tmr.c and Pwm_Tmr.h "
#endif
/* Make sure the software major version number is the same between Pwm_Tmr.c and Pwm_Tmr.h */
#if (PWM_TMR_SW_MAJOR_VERSION != PWM_TMR_H_SW_MAJOR_VERSION)
    #error "Software Major Version Number mismatch between Pwm_Tmr.c and Pwm_Tmr.h "
#endif
/* Make sure the software minor version number is the same between Pwm_Tmr.c and Pwm_Tmr.h */
#if (PWM_TMR_SW_MINOR_VERSION != PWM_TMR_H_SW_MINOR_VERSION)
    #error "Software Minor Version Number mismatch between Pwm_Tmr.c and Pwm_Tmr.h "
#endif
/* Make sure the software patch version number is the same between Pwm_Tmr.c and Pwm_Tmr.h */
#if (PWM_TMR_SW_PATCH_VERSION != PWM_TMR_H_SW_PATCH_VERSION)
    #error "Software Patch Version Number mismatch between Pwm_Tmr.c and Pwm_Tmr.h "
#endif

/* Make sure the vendor id is the same between Pwm_Tmr.c and Pwm_Notif.h */
#if (PWM_TMR_VENDOR_ID != PWM_NOTIF_H_VENDOR_ID)
    #error "Vendor id mismatch between Pwm_Tmr.c and Pwm_Notif.h "
#endif
/* Make sure the AUTOSAR major version number is the same between Pwm_Tmr.c and Pwm_Notif.h */
#if (PWM_TMR_AR_RELEASE_MAJOR_VERSION != PWM_NOTIF_H_AR_RELEASE_MAJOR_VERSION)
    #error "AUTOSAR Major Version Number mismatch between Pwm_Tmr.c and Pwm_Notif.h "
#endif
/* Make sure the AUTOSAR minor version number is the same between Pwm_Tmr.c and Pwm_Notif.h */
#if (PWM_TMR_AR_RELEASE_MINOR_VERSION != PWM_NOTIF_H_AR_RELEASE_MINOR_VERSION)
    #error "AUTOSAR Minor Version Number mismatch between Pwm_Tmr.c and Pwm_Notif.h "
#endif
/* Make sure the AUTOSAR revision version number is the same between Pwm_Tmr.c and Pwm_Notif.h */
#if (PWM_TMR_AR_RELEASE_REVISION_VERSION != PWM_NOTIF_H_AR_RELEASE_REVISION_VERSION)
    #error "AUTOSAR Revision Version Number mismatch between Pwm_Tmr.c and Pwm_Notif.h "
#endif
/* Make sure the software major version number is the same between Pwm_Tmr.c and Pwm_Notif.h */
#if (PWM_TMR_SW_MAJOR_VERSION != PWM_NOTIF_H_SW_MAJOR_VERSION)
    #error "Software Major Version Number mismatch between Pwm_Tmr.c and Pwm_Notif.h "
#endif
/* Make sure the software minor version number is the same between Pwm_Tmr.c and Pwm_Notif.h */
#if (PWM_TMR_SW_MINOR_VERSION != PWM_NOTIF_H_SW_MINOR_VERSION)
    #error "Software Minor Version Number mismatch between Pwm_Tmr.c and Pwm_Notif.h "
#endif
/* Make sure the software patch version number is the same between Pwm_Tmr.c and Pwm_Notif.h */
#if (PWM_TMR_SW_PATCH_VERSION != PWM_NOTIF_H_SW_PATCH_VERSION)
    #error "Software Patch Version Number mismatch between Pwm_Tmr.c and Pwm_Notif.h "
#endif

#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Pwm_Tmr.c and StdRegMacros.h */
    #if (PWM_TMR_AR_RELEASE_MAJOR_VERSION != STD_REG_MACROS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Pwm_Tmr.c and StdRegMacros.h "
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Pwm_Tmr.c and StdRegMacros.h */
    #if (PWM_TMR_AR_RELEASE_MINOR_VERSION != STD_REG_MACROS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Pwm_Tmr.c and StdRegMacros.h "
    #endif
    /* Make sure the AUTOSAR major version number is the same between Pwm_Tmr.c and SchM_Pwm.h */
    #if (PWM_TMR_AR_RELEASE_MAJOR_VERSION != SCHM_PWM_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Pwm_Tmr.c and SchM_Pwm.h "
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Pwm_Tmr.c and SchM_Pwm.h */
    #if (PWM_TMR_AR_RELEASE_MINOR_VERSION != SCHM_PWM_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Pwm_Tmr.c and SchM_Pwm.h "
    #endif
#endif

/* Make sure the vendor id is the same between Pwm_Tmr.c and Dio_Reg.h */
#if (PWM_TMR_VENDOR_ID != DIO_REG_H_VENDOR_ID)
    #error "Vendor id mismatch between Pwm_Tmr.c and Dio_Reg.h "
#endif
/* Make sure the AUTOSAR major version number is the same between Pwm_Tmr.c and Dio_Reg.h */
#if (PWM_TMR_AR_RELEASE_MAJOR_VERSION != DIO_REG_H_AR_RELEASE_MAJOR_VERSION)
    #error "AUTOSAR Major Version Number mismatch between Pwm_Tmr.c and Dio_Reg.h "
#endif
/* Make sure the AUTOSAR minor version number is the same between Pwm_Tmr.c and Dio_Reg.h */
#if (PWM_TMR_AR_RELEASE_MINOR_VERSION != DIO_REG_H_AR_RELEASE_MINOR_VERSION)
    #error "AUTOSAR Minor Version Number mismatch between Pwm_Tmr.c and Dio_Reg.h "
#endif
/* Make sure the AUTOSAR revision version number is the same between Pwm_Tmr.c and Dio_Reg.h */
#if (PWM_TMR_AR_RELEASE_REVISION_VERSION != DIO_REG_H_AR_RELEASE_REVISION_VERSION)
    #error "AUTOSAR Revision Version Number mismatch between Pwm_Tmr.c and Dio_Reg.h "
#endif
/* Make sure the software major version number is the same between Pwm_Tmr.c and Dio_Reg.h */
#if (PWM_TMR_SW_MAJOR_VERSION != DIO_REG_H_SW_MAJOR_VERSION)
    #error "Software Major Version Number mismatch between Pwm_Tmr.c and Dio_Reg.h "
#endif
/* Make sure the software minor version number is the same between Pwm_Tmr.c and Dio_Reg.h */
#if (PWM_TMR_SW_MINOR_VERSION != DIO_REG_H_SW_MINOR_VERSION)
    #error "Software Minor Version Number mismatch between Pwm_Tmr.c and Dio_Reg.h "
#endif
/* Make sure the software patch version number is the same between Pwm_Tmr.c and Dio_Reg.h */
#if (PWM_TMR_SW_PATCH_VERSION != DIO_REG_H_SW_PATCH_VERSION)
    #error "Software Patch Version Number mismatch between Pwm_Tmr.c and Dio_Reg.h "
#endif

/**************************************************************************
                    MACRO DEFINITION
**************************************************************************/
/** @defgroup PWM_Macros
  @{
*/

#define PWM_TMR_CHANNEL_MASK_BITS ((uint8)0x03)
#define PWM_TMR_MODULE_MASK_BITS  ((uint8)0x0C)
#define PWM_TMR_MODULE_SHIFT_VAL  ((uint8)0x02)

/**@} end of group PWM_Macros */

/**************************************************************************
                    GLOBAL VARIABLE
**************************************************************************/
/** @defgroup PWM_Variable
  @{
*/

/**@} end of group PWM_Variable */

#define PWM_START_SEC_VAR_NO_INIT_8
#include "Pwm_MemMap.h"

/** @defgroup PWM_Variable
  @{
*/

#if (STD_ON == PWM_FAULT_CHECK_SUPPORTED)
/** check fault state */
static VAR(uint8, PWM_VAR) s_FaultCheck;
#endif

#if ((STD_ON == PWM_SET_OUTPUT_TO_IDLE_API) || (STD_ON == PWM_LOW_POWER_STATE_ENABLE))
/** indicate pwm tmr channel state : runing/idle */
static VAR(uint8, PWM_VAR) s_ChState[PWM_TMR_CHANNELS_NUM];
#endif

#if ((STD_ON == PWM_FAULT_CHECK_SUPPORTED) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
static volatile VAR(Pwm_TmrNotifyConditionType, PWM_VAR) s_NotifToChannelMap[PWM_TMR_CHANNEL_MAXNUM];
#endif

/**@} end of group PWM_Variable */

#define PWM_STOP_SEC_VAR_NO_INIT_8
#include "Pwm_MemMap.h"

#define PWM_START_SEC_VAR_NO_INIT_16
#include "Pwm_MemMap.h"

/** @defgroup PWM_Variable
  @{
*/

#if ((STD_ON == PWM_GET_CHANNEL_DUTYCYCLE) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
/** pwm tmr channel duty cycle value */
static VAR(uint16, PWM_VAR) s_ChDutyCycle[PWM_TMR_CHANNELS_NUM];
#endif

/** pwm tmr instance period value */
static VAR(uint16, PWM_VAR) s_ChPeriod[PWM_TMR_MODULE_NUM];

/** pwm tmr instance modulo register value */
static VAR(uint16, PWM_VAR) s_ChModValue[PWM_TMR_MODULE_NUM];

/**@} end of group PWM_Variable */

#define PWM_STOP_SEC_VAR_NO_INIT_16
#include "Pwm_MemMap.h"

#define PWM_START_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Pwm_MemMap.h"

/** @defgroup PWM_Variable
  @{
*/

#if ((STD_ON == PWM_SET_OUTPUT_TO_IDLE_API) || (STD_ON == PWM_DE_INIT_API))
/** indicate pwm tmr channel idle level */
static VAR(Pwm_OutputStateType, PWM_VAR) s_ChIdleStatus[PWM_TMR_CHANNELS_NUM];
#endif

#if (STD_ON == PWM_NOTIFICATION_SUPPORTED) 
/** indicate pwm tmr channel polarity level */
static VAR(Pwm_OutputStateType, PWM_VAR) s_ChPolarityStatus[PWM_TMR_CHANNELS_NUM];
#endif

/**@} end of group PWM_Variable */

#define PWM_STOP_SEC_VAR_NO_INIT_UNSPECIFIED
#include "Pwm_MemMap.h"

/**************************************************************************
                    FUNCTION DECLARATION
**************************************************************************/
#define PWM_START_SEC_CODE
#include "Pwm_MemMap.h"

/** @defgroup PWM_Fuctions
  @{
*/

LOCAL_INLINE FUNC(uint16, PWM_CODE) Pwm_Tmr_CalculateCCnRegValue(VAR(Pwm_TmrInstanceType, AUTOMATIC) InstanceId,
                                                                 VAR(uint16, AUTOMATIC) DutyCycle,
                                                                 VAR(Pwm_ChAlignType, AUTOMATIC) AlignStyle);

LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_Tmr_SetDutyCycleReg(VAR(Pwm_TmrInstanceType, AUTOMATIC) InstanceId,
                                                          VAR(Pwm_TmrChIdType, AUTOMATIC) ChId,
                                                          VAR(uint16, AUTOMATIC) DutyCycle,
                                                          VAR(Pwm_ChAlignType, AUTOMATIC) AlignStyle);

LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_Tmr_CalculatePeriodRegValue(VAR(Pwm_TmrInstanceType, AUTOMATIC) InstanceId,
                                                                  VAR(Pwm_PeriodType, AUTOMATIC) Period,
                                                                  VAR(Pwm_ChAlignType, AUTOMATIC) AlignStyle);

#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_Tmr_DisableCmpInterruptIrq(VAR(Pwm_TmrInstanceType, AUTOMATIC) InstanceId,
                                                                 VAR(Pwm_TmrChIdType, AUTOMATIC) ChId);

LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_Tmr_InvokeNotification(VAR(Pwm_TmrChIdType, AUTOMATIC) ChId,
                                                             VAR(Pwm_TmrInstanceType, AUTOMATIC) TmrModule);
#endif

/**************************************************************************
                    LOCAL FUNCTION
**************************************************************************/
/*!
* @brief         This function is used to calculates the value of the CHnV register
*
* @param[in]     InstanceId    - TMR instance id
* @param[in]     DutyCycle     - duty cycle value
* @param[in]     AlignStyle    - alignment class
* @param[out]    None
* @param[in,out] None
*
* @retval        uint16 : CHnV register value
*/
LOCAL_INLINE FUNC(uint16, PWM_CODE) Pwm_Tmr_CalculateCCnRegValue(VAR(Pwm_TmrInstanceType, AUTOMATIC) InstanceId,
                                                                 VAR(uint16, AUTOMATIC) DutyCycle,
                                                                 VAR(Pwm_ChAlignType, AUTOMATIC) AlignStyle)
{
    VAR(uint16, AUTOMATIC) CCnRegValue = (uint16)0U;

    switch (DutyCycle)
    {
        case (uint16)0U:   /* duty cycle equal to 0 */
            CCnRegValue = (uint16)0U;
            (void)AlignStyle;
            break;

        case (uint16)0x8000U:   /* duty cycle equal to 100% */
            CCnRegValue = s_ChModValue[InstanceId] + 1U;
            (void)AlignStyle;
            break;

        default:   /* duty cycle between 0 to 100% */
            if((PWM_CENTER_ALIGN == AlignStyle) || 
               (PWM_CENTER_SYNCHRONOUS_ALIGN == AlignStyle) || 
               (PWM_CENTER_COMPLEMENTARY_ALIGN == AlignStyle))
               {
                   CCnRegValue = (uint16)((((uint32)s_ChPeriod[InstanceId] * (uint32)DutyCycle) >> 15U) >> 1U);
               }
               else
               {
                   CCnRegValue = (uint16)(((uint32)s_ChPeriod[InstanceId] * (uint32)DutyCycle) >> 15U);
               }
            break;
    }

    return CCnRegValue;
}

/*!
* @brief         This function is used to set registers about duty cycle
*
* @param[in]     InstanceId    - TMR instance id
* @param[in]     ChId          - pwm channel id
* @param[in]     DutyCycle     - duty cycle value
* @param[in]     AlignStyle    - pwm channel alignement class
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_Tmr_SetDutyCycleReg(VAR(Pwm_TmrInstanceType, AUTOMATIC) InstanceId,
                                                          VAR(Pwm_TmrChIdType, AUTOMATIC) ChId,
                                                          VAR(uint16, AUTOMATIC) DutyCycle,
                                                          VAR(Pwm_ChAlignType, AUTOMATIC) AlignStyle)
{
    /* CHnV Register Value */
    VAR(uint16, AUTOMATIC) CCnRegValue = (uint16)0U;

#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
    VAR(Pwm_TmrChIdType, AUTOMATIC) nLogicalChannelIndex =
      ((Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM * (Pwm_TmrChIdType)InstanceId) + ChId;

    if ((((uint16)0U) == DutyCycle) || (((uint16)0x8000U) == DutyCycle))
    {
        if(PWM_TMR_INT_CONDITION_NO_EDGE == ((s_NotifToChannelMap[nLogicalChannelIndex]) & PWM_TMR_UIFLG_EDGE))
        {
            /* do nothing */
        }
        else /* indicate no overflow notifications */
        {
            s_NotifToChannelMap[nLogicalChannelIndex] |= PWM_TMR_UIFLG_NO_EDGE_NOTIF;
        }
#if (STD_ON == PWM_FAULT_CHECK_SUPPORTED)
        if(PWM_TMR_INT_CONDITION_NO_EDGE == ((s_NotifToChannelMap[nLogicalChannelIndex]) & PWM_TMR_UIFLG_FAULT_IDLE_STATE))
        {
            /* do nothing */
        }
        else /* Clear fault notification flag */
        {
            s_NotifToChannelMap[nLogicalChannelIndex] &= (uint8)~(PWM_TMR_UIFLG_FAULT_IDLE_STATE);
        }
#endif
        /* Disable compare interrupts for pwm channel */
        Pwm_Tmr_DisableCmpInterruptIrq(InstanceId, ChId);
    }
    else
    {
        /* Enable compare interrupts */
        if(PWM_TMR_INT_CONDITION_NO_EDGE == ((s_NotifToChannelMap[nLogicalChannelIndex]) & PWM_TMR_UIFLG_EDGE))
        {
            /* do nothing */
        }
        else 
        {
            /* indicate channel using tof interrupt with notification */
            s_NotifToChannelMap[nLogicalChannelIndex] &= (uint8)~(PWM_TMR_UIFLG_NO_EDGE_NOTIF);
            /* Enable Updata interrupt interrupt */
            REG_BIT_SET32(TMR_DIEN_REG_ADDR(InstanceId + 1U), TMR_DIEN_UIEN_MASK);
        }

        if(PWM_TMR_INT_CONDITION_NO_EDGE == ((s_NotifToChannelMap[nLogicalChannelIndex]) & PWM_TMR_UIFLG_FAULT_IDLE_STATE))
        {
            /* do nothing */
        }
        else 
        {
            /* Clear fault notification flag */
            s_NotifToChannelMap[nLogicalChannelIndex] &= (uint8)~(PWM_TMR_UIFLG_FAULT_IDLE_STATE);
            /* Disable match compare interrupts */
            Pwm_Tmr_DisableCmpInterruptIrq(InstanceId, ChId);
        }

        if(PWM_TMR_INT_CONDITION_NO_EDGE == ((s_NotifToChannelMap[nLogicalChannelIndex]) & PWM_TMR_CCXIFLG_EDGE))
        {
            /* do nothing */
        }
        else /* Enable interrupts */
        {
            REG_BIT_SET32(TMR_DIEN_REG_ADDR(InstanceId + 1U), (uint32)2U << ChId);
        }
    }
#endif

    /* calcualte CHnV value and write register */
    CCnRegValue = Pwm_Tmr_CalculateCCnRegValue(InstanceId, DutyCycle, AlignStyle);

    if(ChId == 0U)
    {
        REG_WRITE32(TMR_CC1_REG_ADDR(InstanceId + 1U), (uint32)s_ChModValue[InstanceId] + (uint32)1U - (uint32)CCnRegValue);
    }
    else if(ChId == 1U)
    {
        REG_WRITE32(TMR_CC2_REG_ADDR(InstanceId + 1U), (uint32)s_ChModValue[InstanceId] + (uint32)1U - (uint32)CCnRegValue);
    }
    else if(ChId == 2U)
    {
        REG_WRITE32(TMR_CC3_REG_ADDR(InstanceId + 1U), (uint32)s_ChModValue[InstanceId] + (uint32)1U - (uint32)CCnRegValue);
    }
    else if(ChId == 3U)
    {
        REG_WRITE32(TMR_CC4_REG_ADDR(InstanceId + 1U), (uint32)s_ChModValue[InstanceId] + (uint32)1U - (uint32)CCnRegValue);
    }
    else
    {
        /* do nothing */
    }
}

/*!
* @brief         This function is used to calculate the value of the period register
*
* @param[in]     InstanceId    - TMR instance id
* @param[in]     Period        - period value
* @param[in]     AlignStyle    - alignment class
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_Tmr_CalculatePeriodRegValue(VAR(Pwm_TmrInstanceType, AUTOMATIC) InstanceId,
                                                                  VAR(Pwm_PeriodType, AUTOMATIC) Period,
                                                                  VAR(Pwm_ChAlignType, AUTOMATIC) AlignStyle)
{
    switch (AlignStyle)
    {
        case PWM_CENTER_ALIGN:
            s_ChModValue[InstanceId] = (uint16)Period >> 1U;
            break;
        case PWM_CENTER_SYNCHRONOUS_ALIGN:
            s_ChModValue[InstanceId] = (uint16)Period >> 1U;
            break;
        case PWM_CENTER_COMPLEMENTARY_ALIGN:
            s_ChModValue[InstanceId] = (uint16)Period >> 1U;
            break;
        default:
            s_ChModValue[InstanceId] = (uint16)Period - (uint16)1U;
            break;
    }

    s_ChPeriod[InstanceId] = (uint16)Period;
}

#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
/*!
* @brief         This function is used to disable pwm tmr interrupt on a specified channel and clears its flags.
*
* @param[in]     InstanceId    -TMR instance id
* @param[in]     ChId          -pwm channel id
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_Tmr_DisableCmpInterruptIrq(VAR(Pwm_TmrInstanceType, AUTOMATIC) InstanceId,
                                                                 VAR(Pwm_TmrChIdType, AUTOMATIC) ChId)
{
    VAR(Pwm_TmrChIdType, AUTOMATIC) chMaxNumber = (Pwm_TmrChIdType)0U;
    VAR(Pwm_TmrChIdType, AUTOMATIC) firstChId = (Pwm_TmrChIdType)0U;
    VAR(Pwm_TmrChIdType, AUTOMATIC) chCount = (Pwm_TmrChIdType)0U;
    VAR(Pwm_OutputStateType, AUTOMATIC) edgeEnable = PWM_LOW;
    VAR(Pwm_TmrNotifyConditionType, AUTOMATIC) intEdge = (Pwm_TmrNotifyConditionType)0U;

    /* Disable pwm channel interrupt */
    REG_BIT_CLEAR32(TMR_DIEN_REG_ADDR(InstanceId + 1U), (uint32)2U << ChId);
    /* Clear pwm channel interrupt flag */
    REG_BIT_CLEAR32(TMR_STS_REG_ADDR(InstanceId + 1U), (uint32)2U << ChId);

    /* Get the instance first channel id */
    firstChId = ((Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM * (Pwm_TmrChIdType)InstanceId);
    /* Get the instance max channel id */
    chMaxNumber = (firstChId + (Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM);

    /* Check if it is possible to disable overflow interrupt */
    for(chCount = firstChId; chCount < chMaxNumber; chCount++)
    {
#if (STD_ON == PWM_OVERFLOW_CHECK_SUPPORTED)
        intEdge = s_NotifToChannelMap[chCount] & PWM_TMR_UIFLG_EDGE;
#endif
        if(PWM_TMR_INT_CONDITION_NO_EDGE != intEdge)
        {
            edgeEnable = PWM_HIGH;
            break;
        }
        else
        {
            /* do nothing */
        }
    }

    /* If no channel enabled for overflow interrupt */
    if(PWM_LOW == edgeEnable)
    {
        REG_BIT_CLEAR32(TMR_DIEN_REG_ADDR(InstanceId + 1U), TMR_DIEN_UIEN_MASK);
    }
    else
    {
        /* do nothing */
    }

    /* Clear pwm channel overflow interrupt flag */
    REG_BIT_CLEAR32(TMR_STS_REG_ADDR(InstanceId + 1U), TMR_STS_UIFLG_MASK);
}

/*!
* @brief          This function is used to invoke notification function
*
* @param[in]      ChId            -pwm channel id
* @param[in]      TmrModule       -tmr instance id
*
* @retval         None
*
*/
LOCAL_INLINE FUNC(void, PWM_CODE) Pwm_Tmr_InvokeNotification(VAR(Pwm_TmrChIdType, AUTOMATIC) ChId,
                                                             VAR(Pwm_TmrInstanceType, AUTOMATIC) TmrModule)
{
    VAR(Pwm_TmrChIdType, AUTOMATIC) chModOffset = (Pwm_TmrChIdType)0U;
    VAR(Pwm_TmrNotifyConditionType, AUTOMATIC) edgeState = (Pwm_TmrNotifyConditionType)0U;
    VAR(Pwm_TmrChIdType, AUTOMATIC) chModOffsetCal = (Pwm_TmrChIdType)0U;

    /* Clear CCXIFLG bit */
    REG_BIT_CLEAR32(TMR_STS_REG_ADDR(TmrModule + 1U), (uint32)1U << (ChId + 1U));
    /* get channel id offset value */
    chModOffset = ((Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM * (Pwm_TmrChIdType)TmrModule) + ChId;
    /* get channel edge state */
    edgeState = ((s_NotifToChannelMap[chModOffset]) & PWM_TMR_CCXIFLG_EDGE);

    if(PWM_TMR_INT_CONDITION_NO_EDGE != edgeState)
    {
        chModOffsetCal = (Pwm_TmrChIdType) chModOffset;
        Pwm_ExecuteNotificationFunction((Pwm_ChannelType)(chModOffsetCal) + PWM_CHANNELS_IN_HW_FIRST_MAPINDEX);
    }
    else
    {
        /* do nothing */
    }
}
#endif

/**************************************************************************
                    GLOBAL FUNCTION
**************************************************************************/
/*!
* @brief          Initialization function of the PWM TMR Low-level driver.
*
* @param[in]      pTmrIpCfgPtr    -pointer to the tmr channel configuration
* @param[out]     None
* @param[in,out]  None
*
* @retval         None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_Init(CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* used for tmr count */
    VAR(uint8, AUTOMATIC) tmrCount = 0U;
    VAR(uint32, AUTOMATIC) ccENMask = 0U;
    VAR(uint32, AUTOMATIC) ccnENMask = 0U;
    /* used for channel count */
    VAR(uint8, AUTOMATIC) chCount = 0U;
    /* TMR internal instance id */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) internalTmrId = (uint8)0U;
    /* TMR hardware instance id */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) hwInstanceId = (uint8)0U;
    /* Total number of used tmr instance */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) numberOfUsedTmr = pTmrIpCfgPtr->cfgTmrNumber;
    /* Total number channel belong to Tmr */
    VAR(Pwm_TmrChIdType, AUTOMATIC) tmrChNumTotal = pTmrIpCfgPtr->cfgChNumber;
    /* Default period value */
    VAR(uint16, AUTOMATIC) defaultPeriodVal = (uint16)0U;
    /* hardware channel id */
    VAR(Pwm_TmrChIdType, AUTOMATIC) hwChannelId = (Pwm_TmrChIdType)0U;
    /* Pointer to Tmr channel configuration struct */
    P2CONST(Pwm_TmrChCfgType, AUTOMATIC, PWM_APPL_CONST) pChCfgPtr = NULL_PTR;
    /* Pointer to Tmr register struct */
    P2CONST(Pwm_TmrRegValType, AUTOMATIC, PWM_APPL_CONST) pRegValPtr = NULL_PTR;

#if ((STD_ON == PWM_FAULT_CHECK_SUPPORTED) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
    for(chCount = 0U; chCount < PWM_TMR_CHANNEL_MAXNUM; chCount++)
    {
        s_NotifToChannelMap[chCount] = PWM_TMR_INT_CONDITION_NO_EDGE;
    }
#endif
#if ((STD_ON == PWM_GET_CHANNEL_DUTYCYCLE) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
    for(chCount = 0U; chCount < PWM_TMR_CHANNELS_NUM; chCount++)
    {
        s_ChDutyCycle[chCount] = (uint8)0U;
    }
#endif
#if (STD_ON == PWM_FAULT_CHECK_SUPPORTED)
    s_FaultCheck = (uint8)0U;
#endif

    for (tmrCount = 0U; tmrCount < numberOfUsedTmr; tmrCount++)
    {
        pRegValPtr = &(*pTmrIpCfgPtr->pCfgTmrPtr)[tmrCount];
        hwInstanceId = pRegValPtr->tmrName; /* Get tmr name */

        if(PWM_TMR1 != hwInstanceId)
        {
            /* nothing to do */
        }
        else 
        {
            if(0U == REG_BIT_GET32(TMR_BDT_REG_ADDR(hwInstanceId + 1U), TMR_BDT_LOCKCFG_MASK))
            {
                /* nothing to do */
            }
            else
            {
                /* unlock register to write */
                REG_BIT_CLEAR32(TMR_BDT_REG_ADDR(hwInstanceId + 1U), TMR_BDT_LOCKCFG_MASK);
            }
        }

        /* set CAMSEL , CNTDIR and CLKDIV bit */
        REG_WRITE32(TMR_CTRL1_REG_ADDR(hwInstanceId + 1U), pRegValPtr->tmrCtrl1);
        /* An interrupt is generated only when the counter overflows or underflows */
        REG_BIT_SET32(TMR_CTRL1_REG_ADDR(hwInstanceId + 1U), TMR_CTRL1_URSSEL_MASK);
        /* Set TMR prescaler */
        REG_WRITE32(TMR_PSC_REG_ADDR(hwInstanceId + 1U), pRegValPtr->tmrPsc);
        /* disable slave mode */
        REG_WRITE32(TMR_SMCTRL_REG_ADDR(hwInstanceId + 1U), 0U);
        /* set control event register */
        REG_WRITE32(TMR_CEG_REG_ADDR(hwInstanceId + 1U), 0U);

#if (STD_ON == PWM_SINGLE_PULSE_MODE)
        REG_BIT_SET32(TMR_CTRL1_REG_ADDR(hwInstanceId + 1U), TMR_CTRL1_SPMEN_MASK);
#else
        REG_BIT_CLEAR32(TMR_CTRL1_REG_ADDR(hwInstanceId + 1U), TMR_CTRL1_SPMEN_MASK);
#endif
        if(PWM_TMR1 == hwInstanceId)
        {
            REG_WRITE32(TMR_BDT_REG_ADDR(hwInstanceId + 1U), ((pRegValPtr->tmrBdt) & (~TMR_BDT_BRKEN_MASK)));
            REG_WRITE32(TMR_REPCNT_REG_ADDR(hwInstanceId + 1U), PWM_REPEAT_NUMBER);
        }
        else
        {
            /* do nothing */
        }

        /* enable updata buffer strategy */
        REG_BIT_CLEAR32(TMR_CTRL1_REG_ADDR(hwInstanceId + 1U), TMR_CTRL1_UD_MASK);
#if (STD_ON == PWM_PERIOD_UPDATED_END_PERIOD)
        REG_BIT_SET32(TMR_CTRL1_REG_ADDR(hwInstanceId + 1U), TMR_CTRL1_ARPEN_MASK);
#else
        REG_BIT_CLEAR32(TMR_CTRL1_REG_ADDR(hwInstanceId + 1U), TMR_CTRL1_ARPEN_MASK);
#endif
        for (chCount = 0U; chCount < tmrChNumTotal; chCount++)
        {
            pChCfgPtr = &(*pTmrIpCfgPtr->pCfgChPtr)[chCount];
            /* The tmr name where the channel is located */
            internalTmrId = (Pwm_TmrInstanceType)(((pChCfgPtr->pwmChName) & PWM_TMR_MODULE_MASK_BITS) >> PWM_TMR_MODULE_SHIFT_VAL);

            if (internalTmrId == hwInstanceId)
            {
#if ((STD_ON == PWM_GET_CHANNEL_DUTYCYCLE) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
                s_ChDutyCycle[chCount] = pChCfgPtr->pwmChDutyCycle;
#endif
#if (STD_ON == PWM_NOTIFICATION_SUPPORTED) 
                s_ChPolarityStatus[chCount] = pChCfgPtr->pwmChPolarity;
#endif
#if ((STD_ON == PWM_SET_OUTPUT_TO_IDLE_API) || (STD_ON == PWM_DE_INIT_API))
                s_ChIdleStatus[chCount] = pChCfgPtr->pwmChIdleState;
#endif
                hwChannelId = ((pChCfgPtr->pwmChName) & PWM_TMR_CHANNEL_MASK_BITS); /* Channel number within tmr: 0/1/2/3 */
#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
                Pwm_Tmr_DisableCmpInterruptIrq(hwInstanceId, hwChannelId);
#endif
#if ((STD_ON == PWM_SET_OUTPUT_TO_IDLE_API) || (STD_ON == PWM_LOW_POWER_STATE_ENABLE))
                s_ChState[chCount] = (uint8)PWM_TMR_CHANNEL_IS_RUNNING;
#endif
                ccnENMask = TMR_CCEN_CC1NEN_MASK << (0x04U * hwChannelId);
                ccENMask  = TMR_CCEN_CC1EN_MASK << (0x04U * hwChannelId);

                defaultPeriodVal = pRegValPtr->periodTick;
                Pwm_Tmr_CalculatePeriodRegValue(hwInstanceId, defaultPeriodVal, pChCfgPtr->pwmChAlign);
                Pwm_Tmr_SetDutyCycleReg(hwInstanceId, hwChannelId, pChCfgPtr->pwmChDutyCycle, pChCfgPtr->pwmChAlign);
                REG_WRITE32(TMR_AUTORLD_REG_ADDR(hwInstanceId + 1U), (uint32)(s_ChModValue[hwInstanceId]));

                /* set output mode */
                if((0U == hwChannelId) || (1U == hwChannelId))
                {
                    REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(hwInstanceId + 1U), TMR_CCM1_CC1SEL_MASK << (0x08U * hwChannelId));
                    REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(hwInstanceId + 1U), TMR_CCM1_OC1FEN_MASK << (0x08U * hwChannelId));
#if (STD_ON == PWM_DUTY_CYCLE_UPDATED_END_PERIOD)
                      REG_BIT_SET32(TMR_CCM1_REG_ADDR(hwInstanceId + 1U), TMR_CCM1_OC1PEN_MASK << (0x08U * hwChannelId));
#else
                    REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(hwInstanceId + 1U), TMR_CCM1_OC1PEN_MASK << (0x08U * hwChannelId));
#endif
                    REG_BIT_SET32(TMR_CCM1_REG_ADDR(hwInstanceId + 1U), (uint32)(pChCfgPtr->mode1or2) << ((0x08U * hwChannelId) + 0x04U));
                    REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(hwInstanceId + 1U), TMR_CCM1_OC1CEN_MASK << ((0x08U * hwChannelId) + 0x04U));
                }
                else
                {
                    REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(hwInstanceId + 1U), TMR_CCM2_CC3SEL_MASK << ((0x08U * hwChannelId) - 0x02U));
                    REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(hwInstanceId + 1U), TMR_CCM2_OC3FEN_MASK << ((0x08U * hwChannelId) - 0x02U));
#if (STD_ON == PWM_DUTY_CYCLE_UPDATED_END_PERIOD)
                      REG_BIT_SET32(TMR_CCM2_REG_ADDR(hwInstanceId + 1U), TMR_CCM2_OC3PEN_MASK << ((0x08U * hwChannelId) - 0x02U));
#else
                    REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(hwInstanceId + 1U), TMR_CCM2_OC3PEN_MASK << ((0x08U * hwChannelId) - 0x02U));
#endif
                    REG_BIT_SET32(TMR_CCM2_REG_ADDR(hwInstanceId + 1U), (uint32)(pChCfgPtr->mode1or2) << ((0x08U * (uint8)(hwChannelId - 0x02U)) + 0x04U));
                    REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(hwInstanceId + 1U), TMR_CCM2_OC3CEN_MASK << ((0x08U * (uint8)(hwChannelId - 0x02U)) + 0x04U));
                }

                if(PWM_HIGH == pChCfgPtr->pwmChPolarity)
                {
                    REG_BIT_CLEAR32(TMR_CCEN_REG_ADDR(hwInstanceId + 1U), TMR_CCEN_CC1POL_MASK << (0x04U * hwChannelId));
                }
                else
                {
                    REG_BIT_SET32(TMR_CCEN_REG_ADDR(hwInstanceId + 1U), TMR_CCEN_CC1POL_MASK << (0x04U * hwChannelId));
                }

            if((PWM_EDGE_COMPLEMENTARY_ALIGN == pChCfgPtr->pwmChAlign) || (PWM_CENTER_COMPLEMENTARY_ALIGN == pChCfgPtr->pwmChAlign))
                {
                    if(PWM_HIGH == pChCfgPtr->pwmChPolarity)
                    {
                        REG_BIT_CLEAR32(TMR_CCEN_REG_ADDR(hwInstanceId + 1U), TMR_CCEN_CC1NPOL_MASK << (0x04U * hwChannelId));
                    }
                    else
                    {
                        REG_BIT_SET32(TMR_CCEN_REG_ADDR(hwInstanceId + 1U), TMR_CCEN_CC1NPOL_MASK << (0x04U * hwChannelId));
                    }

                    REG_BIT_SET32(TMR_CCEN_REG_ADDR(hwInstanceId + 1U), ((uint32)ccENMask | (uint32)ccnENMask));
                }
                else if((PWM_EDGE_SYNCHRONOUS_ALIGN == pChCfgPtr->pwmChAlign) || (PWM_CENTER_SYNCHRONOUS_ALIGN == pChCfgPtr->pwmChAlign))
                {
                    if(PWM_HIGH == pChCfgPtr->pwmChPolarity)
                    {
                        REG_BIT_SET32(TMR_CCEN_REG_ADDR(hwInstanceId + 1U), TMR_CCEN_CC1NPOL_MASK << (0x04U * hwChannelId));
                    }
                    else
                    {
                        REG_BIT_CLEAR32(TMR_CCEN_REG_ADDR(hwInstanceId + 1U), TMR_CCEN_CC1NPOL_MASK << (0x04U * hwChannelId));
                    }

                    REG_BIT_SET32(TMR_CCEN_REG_ADDR(hwInstanceId + 1U), ((uint32)ccENMask | (uint32)ccnENMask));
                }
                else
                {
                    REG_BIT_SET32(TMR_CCEN_REG_ADDR(hwInstanceId + 1U), ccENMask);
                }

#if (STD_ON == PWM_FAULT_CHECK_SUPPORTED)
                if(PWM_HIGH == pChCfgPtr->ocLevle)
                {
                    REG_BIT_SET32(TMR_CTRL2_REG_ADDR(hwInstanceId + 1U), TMR_CTRL2_OC1OIS_MASK << (0x02U * hwChannelId));
                }
                else
                {
                    REG_BIT_CLEAR32(TMR_CTRL2_REG_ADDR(hwInstanceId + 1U), TMR_CTRL2_OC1OIS_MASK << (0x02U * hwChannelId));
                }

                if(PWM_HIGH == pChCfgPtr->ocnLevle)
                {
                    REG_BIT_SET32(TMR_CTRL2_REG_ADDR(hwInstanceId + 1U), TMR_CTRL2_OC1NOIS_MASK << (0x02U * hwChannelId));
                }
                else
                {
                    REG_BIT_CLEAR32(TMR_CTRL2_REG_ADDR(hwInstanceId + 1U), TMR_CTRL2_OC1NOIS_MASK << (0x02U * hwChannelId));
                }
#endif
            }
            else
            {
                /* do nothing */
            }
        }

        if(PWM_TMR1 == hwInstanceId)
        {
            REG_BIT_SET32(TMR_BDT_REG_ADDR(hwInstanceId + 1U), (pRegValPtr->tmrBdt) & (TMR_BDT_BRKEN_MASK));
#ifdef PWM_TMR1_FAULT_ISR_USED
            REG_WRITE32(TMR_DIEN_REG_ADDR(hwInstanceId + 1U), TMR_DIEN_BRKIEN_MASK);
#endif
            REG_WRITE32(TMR_STS_REG_ADDR(hwInstanceId + 1U), 0);
        }
        else
        {
            /* do nothing */
        }

        REG_BIT_SET32(TMR_CEG_REG_ADDR(hwInstanceId + 1U), TMR_CEG_UEG_MASK);
        REG_BIT_SET32(TMR_CTRL1_REG_ADDR(hwInstanceId + 1U), TMR_CTRL1_CNTEN_MASK);
    }
}


#if (STD_ON == PWM_DE_INIT_API)
/*!
* @brief         DeInit function of the pwm TMR Low-level driver.
*
* @param[in]     pTmrIpCfgPtr   -pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_DeInit(CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* Pointer to Tmr IP configuration struct */
    P2CONST(Pwm_TmrRegValType, AUTOMATIC, PWM_APPL_CONST) pRegValPtr = NULL_PTR;
    /* TMR hardware instance */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) tmrId = (uint8)0U;
    /* used for count */
    VAR(uint8, AUTOMATIC) index = 0U;

    /* Reset the static variables defined in this file */
#if (STD_ON == PWM_FAULT_CHECK_SUPPORTED)
    s_FaultCheck = (uint8)0U;
#endif
#if ((STD_ON == PWM_SET_OUTPUT_TO_IDLE_API) || (STD_ON == PWM_LOW_POWER_STATE_ENABLE))
    for(index = 0U; index < PWM_TMR_CHANNELS_NUM; index++)
    {
        s_ChState[index] = (uint8)PWM_TMR_CHANNEL_IS_IDLE;
    }
#endif
#if ((STD_ON == PWM_FAULT_CHECK_SUPPORTED) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
    for(index = 0U; index < PWM_TMR_CHANNEL_MAXNUM; index++)
    {
        s_NotifToChannelMap[index] = PWM_TMR_INT_CONDITION_NO_EDGE;
    }
#endif
#if ((STD_ON == PWM_GET_CHANNEL_DUTYCYCLE) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
    for(index = 0U; index < PWM_TMR_CHANNELS_NUM; index++)
    {
        s_ChDutyCycle[index] = (uint16)0U;
    }
#endif
    for(index = 0U; index < PWM_TMR_MODULE_NUM; index++)
    {
        s_ChPeriod[index] = (uint16)0U;
        s_ChModValue[index] = (uint16)0U;
    }
    for(index = 0U; index < PWM_TMR_CHANNELS_NUM; index++)
    {
        s_ChIdleStatus[index] = PWM_LOW;
    }
#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
    for(index = 0U; index < PWM_TMR_CHANNELS_NUM; index++)
    {
        s_ChPolarityStatus[index] = PWM_LOW;
    }
#endif

    /* Reset TMRx registers values */
    for (index = 0U; index < (pTmrIpCfgPtr->cfgTmrNumber); index++)
    {
        /* Get pointer of Tmr configuration struct */
        pRegValPtr = &(*pTmrIpCfgPtr->pCfgTmrPtr)[index];
        /* get tmr hardware instance */
        tmrId = pRegValPtr->tmrName;
        /* Reset the tmr modules */
        switch (tmrId)
        {
            case PWM_TMR1:
                Mcu_Rcm_OperationPeriphReset(ENABLE, RCM_APB2_PERIPH, RCM_AHBRST2_TMR1);
                Mcu_Rcm_OperationPeriphReset(DISABLE, RCM_APB2_PERIPH, RCM_AHBRST2_TMR1);
                break;
            case PWM_TMR2:
                Mcu_Rcm_OperationPeriphReset(ENABLE, RCM_APB1_PERIPH, RCM_AHBRST1_TMR2);
                Mcu_Rcm_OperationPeriphReset(DISABLE, RCM_APB1_PERIPH, RCM_AHBRST1_TMR2);
                break;
            case PWM_TMR3:
                Mcu_Rcm_OperationPeriphReset(ENABLE, RCM_APB1_PERIPH, RCM_AHBRST1_TMR3);
                Mcu_Rcm_OperationPeriphReset(DISABLE, RCM_APB1_PERIPH, RCM_AHBRST1_TMR3);
                break;
            case PWM_TMR4:
                Mcu_Rcm_OperationPeriphReset(ENABLE, RCM_APB1_PERIPH, RCM_AHBRST1_TMR4);
                Mcu_Rcm_OperationPeriphReset(DISABLE, RCM_APB1_PERIPH, RCM_AHBRST1_TMR4);
                break;
            default:
                {
                    /* do nothing */
                }
                break;
        }
    }
}
#endif

#if ((STD_ON == PWM_SET_DUTY_CYCLE_API) || (STD_ON == PWM_SET_DUTY_CYCLE_SWSYNC))
/*!
* @brief         SetDutyCycle function of the pwm TMR Low-level driver.
*
* @param[in]     ChannelNumber      - channel id
* @param[in]     DutyCycle          - target duty cycle value
* @param[in]     pTmrIpCfgPtr       - pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_SetDutyCycle(VAR(uint8, AUTOMATIC) ChannelNumber, VAR(uint16, AUTOMATIC) DutyCycle,
                             CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* Get pointer to Tmr channel configuration struct */
    P2CONST(Pwm_TmrChCfgType, AUTOMATIC, PWM_APPL_CONST) pChCfgPtr = &(*pTmrIpCfgPtr->pCfgChPtr)[ChannelNumber];
    /* get hardware channel id */
    VAR(Pwm_TmrChIdType,  AUTOMATIC) hwChannelId = ((pChCfgPtr->pwmChName) & PWM_TMR_CHANNEL_MASK_BITS);
    /* get tmr instance id that channel belongs to */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) instanceIdChBelongto = (uint8)
                                         (((pChCfgPtr->pwmChName) & PWM_TMR_MODULE_MASK_BITS) >> PWM_TMR_MODULE_SHIFT_VAL);
    /* get channel alignment */
    VAR(Pwm_ChAlignType, AUTOMATIC) chAlignment = pChCfgPtr->pwmChAlign;

    SchM_Enter_Pwm_PWM_CRITICAL_SECTION1();
#if ((STD_ON == PWM_SET_OUTPUT_TO_IDLE_API) || (STD_ON == PWM_LOW_POWER_STATE_ENABLE))
    if((uint8)PWM_TMR_CHANNEL_IS_IDLE == s_ChState[ChannelNumber])
    {
#if (STD_ON == PWM_SET_OUTPUT_TO_IDLE_API)
        /* Set channel to idle state */
        if(PWM_HIGH == pChCfgPtr->pwmChIdleState)
        {
            if((0U == hwChannelId) || (1U == hwChannelId))
            {
                REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * hwChannelId) + 0x04U));
                REG_BIT_SET32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_HIGH_LEVEL << ((0x08U * hwChannelId) + 0x04U));
            }
            else
            {
                REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
                REG_BIT_SET32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_HIGH_LEVEL << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
            }
        }
        else
        {
            if((0U == hwChannelId) || (1U == hwChannelId))
            {
                REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * hwChannelId) + 0x04U));
                REG_BIT_SET32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_LOW_LEVEL << ((0x08U * hwChannelId) + 0x04U));
            }
            else
            {
                REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
                REG_BIT_SET32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_LOW_LEVEL << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
            }
        }
#endif
        s_ChState[ChannelNumber] = (uint8)PWM_TMR_CHANNEL_IS_RUNNING;
    }
    else
    {
        /* do nothing */
    }
#endif

    Pwm_Tmr_SetDutyCycleReg(instanceIdChBelongto, hwChannelId, DutyCycle, chAlignment);

#if ((STD_ON == PWM_GET_CHANNEL_DUTYCYCLE) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
    s_ChDutyCycle[ChannelNumber] = DutyCycle;
#endif
    SchM_Exit_Pwm_PWM_CRITICAL_SECTION1();
}
#endif

#if ((STD_ON == PWM_SET_PERIOD_AND_DUTY_API) || (STD_ON == PWM_SET_PERIOD_AND_DUTY_SWSYNC))
/*!
* @brief         SetPeriodAndDuty function of the pwm TMR Low-level driver.
*
* @param[in]     ChannelNumber       - channel id
* @param[in]     Period              - target period value
* @param[in]     DutyCycle           - target duty cycle value
* @param[in]     pTmrIpCfgPtr        - pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_SetPeriodAndDuty(VAR(uint8, AUTOMATIC) ChannelNumber,
                                              VAR(Pwm_PeriodType, AUTOMATIC) Period, VAR(uint16, AUTOMATIC) DutyCycle,
                                     CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* Get pointer to Tmr channel configuration struct */
    P2CONST(Pwm_TmrChCfgType, AUTOMATIC, PWM_APPL_CONST) pChCfgPtr = &(*pTmrIpCfgPtr->pCfgChPtr)[ChannelNumber];
    /* get hardware channel Id */
    VAR(Pwm_TmrChIdType, AUTOMATIC) hwChannelId = ((pChCfgPtr->pwmChName) & PWM_TMR_CHANNEL_MASK_BITS);
    /* get tmr instance id that channel belongs to */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) instanceIdChBelongto = (uint8)
                                         (((pChCfgPtr->pwmChName) & PWM_TMR_MODULE_MASK_BITS) >> PWM_TMR_MODULE_SHIFT_VAL);
    /* get channel edge alignment */
    VAR(Pwm_ChAlignType, AUTOMATIC) chAlignment = pChCfgPtr->pwmChAlign;
#if ((STD_ON == PWM_GET_CHANNEL_DUTYCYCLE) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
    /* duty cycle process value */
    VAR(uint16, AUTOMATIC) dutyCycleProcessVal = (uint16)(((uint16)0U == Period) ? 0U : DutyCycle);
#endif

    SchM_Enter_Pwm_PWM_CRITICAL_SECTION0();
#if ((STD_ON == PWM_SET_OUTPUT_TO_IDLE_API) || (STD_ON == PWM_LOW_POWER_STATE_ENABLE))
    if((uint8)PWM_TMR_CHANNEL_IS_IDLE == s_ChState[ChannelNumber])
    {
#if (STD_ON == PWM_SET_OUTPUT_TO_IDLE_API)
        /* Set channel to idle state */
        if(PWM_HIGH == pChCfgPtr->pwmChIdleState)
        {
            if((0U == hwChannelId) || (1U == hwChannelId))
            {
                REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * hwChannelId) + 0x04U));
                REG_BIT_SET32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_HIGH_LEVEL << ((0x08U * hwChannelId) + 0x04U));
            }
            else
            {
                REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
                REG_BIT_SET32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_HIGH_LEVEL << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
            }
        }
        else
        {
            if((0U == hwChannelId) || (1U == hwChannelId))
            {
                REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * hwChannelId) + 0x04U));
                REG_BIT_SET32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_LOW_LEVEL << ((0x08U * hwChannelId) + 0x04U));
            }
            else
            {
                REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
                REG_BIT_SET32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_LOW_LEVEL << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
            }
        }
#endif
        s_ChState[ChannelNumber] = (uint8)PWM_TMR_CHANNEL_IS_RUNNING;
    }
    else
    {
        /* do nothing */
    }
#endif

    /* calculate period register value and write register */
    Pwm_Tmr_CalculatePeriodRegValue(instanceIdChBelongto, Period, chAlignment);
    REG_WRITE32(TMR_AUTORLD_REG_ADDR(instanceIdChBelongto + 1U), (uint32)(s_ChModValue[instanceIdChBelongto]));
    Pwm_Tmr_SetDutyCycleReg(instanceIdChBelongto, hwChannelId, DutyCycle, chAlignment);
#if ((STD_ON == PWM_GET_CHANNEL_DUTYCYCLE) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
    s_ChDutyCycle[ChannelNumber] = dutyCycleProcessVal;
#endif
    SchM_Exit_Pwm_PWM_CRITICAL_SECTION0();
}
#endif

#if (STD_ON == PWM_SET_OUTPUT_TO_IDLE_API)
/*!
* @brief         SetOutputToIdle function of the pwm TMR Low-level driver.
*
* @param[in]     ChannelNumber       - channel id
* @param[in]     pTmrIpCfgPtr        - pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_SetOutputToIdle(VAR(uint8, AUTOMATIC) ChannelNumber,
                      CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* Get pointer to Tmr channel configuration struct */
    P2CONST(Pwm_TmrChCfgType, AUTOMATIC, PWM_APPL_CONST) pChCfgPtr = &(*pTmrIpCfgPtr->pCfgChPtr)[ChannelNumber];
    /* get hardware channel Id */
    VAR(Pwm_TmrChIdType, AUTOMATIC) hwChannelId = ((pChCfgPtr->pwmChName) & PWM_TMR_CHANNEL_MASK_BITS);
    /* get tmr instance id that channel belongs to */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) instanceIdChBelongto = (uint8)
                                         (((pChCfgPtr->pwmChName) & PWM_TMR_MODULE_MASK_BITS) >> PWM_TMR_MODULE_SHIFT_VAL);


    SchM_Enter_Pwm_PWM_CRITICAL_SECTION2();
    if ((uint8)PWM_TMR_CHANNEL_IS_RUNNING == s_ChState[ChannelNumber])
    {
#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
        /* Disable match compare interrupt */
        Pwm_Tmr_DisableCmpInterruptIrq(instanceIdChBelongto, hwChannelId);
#endif
        /* Set channel to idle state */
        if(PWM_HIGH == pChCfgPtr->pwmChIdleState)
        {
            if((0U == hwChannelId) || (1U == hwChannelId))
            {
                REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * hwChannelId) + 0x04U));
                REG_BIT_SET32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_HIGH_LEVEL << ((0x08U * hwChannelId) + 0x04U));
            }
            else
            {
                REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
                REG_BIT_SET32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_HIGH_LEVEL << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
            }
        }
        else
        {
            if((0U == hwChannelId) || (1U == hwChannelId))
            {
                REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * hwChannelId) + 0x04U));
                REG_BIT_SET32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_LOW_LEVEL << ((0x08U * hwChannelId) + 0x04U));
            }
            else
            {
                REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
                REG_BIT_SET32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_LOW_LEVEL << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
            }
        }
        s_ChState[ChannelNumber] = (uint8)PWM_TMR_CHANNEL_IS_IDLE;
#if ((STD_ON == PWM_GET_CHANNEL_DUTYCYCLE) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
        s_ChDutyCycle[ChannelNumber] = (uint16)PWM_TMR_DUTY_CYCLE_EMPTY;
#endif
    }
    else
    {
        /* do nothing */
    }
    SchM_Exit_Pwm_PWM_CRITICAL_SECTION2();
}
#endif

#if (STD_ON == PWM_GET_OUTPUT_STATE_API)
/*!
* @brief         GetOutputState function of the pwm TMR Low-level driver.
*
* @param[in]     ChannelNumber       - channel id
* @param[in]     pTmrIpCfgPtr        - pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        Pwm_OutputStateType:PWM_LOW/PWM_HIGH
*/
FUNC (Pwm_OutputStateType, PWM_CODE) Pwm_Tmr_GetOutputState(VAR(uint8, AUTOMATIC) ChannelNumber,
                           CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* Get pointer to Tmr channel configuration struct */
    P2CONST(Pwm_TmrChCfgType, AUTOMATIC, PWM_APPL_CONST) pChCfgPtr = &(*pTmrIpCfgPtr->pCfgChPtr)[ChannelNumber];
    /* channel output level */
    VAR(Pwm_OutputStateType, AUTOMATIC) chOutputLevel = PWM_HIGH;

    VAR(uint32, AUTOMATIC) regResult = 0U;
    VAR(uint8, AUTOMATIC) count = 0U;
    VAR(uint8, AUTOMATIC) portInstance = 0U;
    VAR(uint8, AUTOMATIC) pinNumber = 0U;

    for(count = 0U; count < PORT_MAX_CONFIG_PIN_COUNT; count++)
    {
        if(pChCfgPtr->pwmpin == g_portConfig.pinNum[count].pinId)
        {
            portInstance = (uint8)(g_portConfig.pinNum[count].portId);
            pinNumber = (uint8)(g_portConfig.pinNum[count].portPinId);
            break;
        }
        else
        {
            /* do nothing */
        }
    }

    regResult = REG_BIT_GET32(GPIO_IDATA_REG_ADDR(portInstance), ((uint32)1U << pinNumber));

    if(regResult == 0U)
    {
        chOutputLevel = PWM_LOW;
    }
    else
    {
        chOutputLevel = PWM_HIGH;
    }

    return chOutputLevel;
}
#endif

#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
/*!
* @brief         DisableNotification function of the pwm TMR Low-level driver.
*
* @param[in]     ChannelNumber       - channel id
* @param[in]     pTmrIpCfgPtr        - pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_DisableNotification(VAR(uint8, AUTOMATIC) ChannelNumber,
                      CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* Get pointer to Tmr channel configuration struct */
    P2CONST(Pwm_TmrChCfgType, AUTOMATIC, PWM_APPL_CONST) pChCfgPtr = &(*pTmrIpCfgPtr->pCfgChPtr)[ChannelNumber];
    /* get hardware channel Id */
    VAR(Pwm_TmrChIdType, AUTOMATIC) hwChannelId = ((pChCfgPtr->pwmChName) & PWM_TMR_CHANNEL_MASK_BITS);
    /* get tmr instance id that channel belongs to */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) instanceIdChBelongto = (uint8)
                                        (((pChCfgPtr->pwmChName) & PWM_TMR_MODULE_MASK_BITS) >> PWM_TMR_MODULE_SHIFT_VAL);

    s_NotifToChannelMap[((Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM * (Pwm_TmrChIdType)instanceIdChBelongto)
                               + hwChannelId] = PWM_TMR_INT_CONDITION_NO_EDGE;

    SchM_Enter_Pwm_PWM_CRITICAL_SECTION3();
    /* disable match compare interrupt */
    Pwm_Tmr_DisableCmpInterruptIrq(instanceIdChBelongto, hwChannelId);
    SchM_Exit_Pwm_PWM_CRITICAL_SECTION3();
}

/*!
* @brief         EnableNotification function of the pwm TMR Low-level driver.
*
* @param[in]     ChannelNumber       - channel id
* @param[in]     Notification        - edge class to cause notification
* @param[in]     pTmrIpCfgPtr        - pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_EnableNotification
                      (VAR(uint8, AUTOMATIC) ChannelNumber, VAR (Pwm_EdgeNotificationType, AUTOMATIC) Notification,
                       CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* Get pointer to Tmr channel configuration struct */
    P2CONST(Pwm_TmrChCfgType, AUTOMATIC, PWM_APPL_CONST) pChCfgPtr = &(*pTmrIpCfgPtr->pCfgChPtr)[ChannelNumber];
    /* Get hardware channel Id */
    VAR(Pwm_TmrChIdType, AUTOMATIC) hwChannelId = ((pChCfgPtr->pwmChName) & PWM_TMR_CHANNEL_MASK_BITS);
    /* Get Tmr instance id that channel belongs to */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) instanceIdChBelongto = (uint8)
                                        (((pChCfgPtr->pwmChName) & PWM_TMR_MODULE_MASK_BITS) >> PWM_TMR_MODULE_SHIFT_VAL);
    /* Get channel porality */
    VAR(Pwm_OutputStateType, AUTOMATIC) chPolarity = s_ChPolarityStatus[ChannelNumber];
    /* channel id offset value */
    VAR(Pwm_TmrChIdType, AUTOMATIC) chModOffset = (Pwm_TmrChIdType)0U;
    /* calcualte edge */
    VAR(Pwm_TmrNotifyConditionType, AUTOMATIC) edgeCal = PWM_TMR_INT_CONDITION_NO_EDGE;

    SchM_Enter_Pwm_PWM_CRITICAL_SECTION4();
    /* Clear CHEVFLG flag */
    REG_BIT_CLEAR32(TMR_STS_REG_ADDR(instanceIdChBelongto + 1U), (uint32)1U << (hwChannelId + 1U));
    /* Clear CFGTMROFLG flag */
    REG_BIT_CLEAR32(TMR_STS_REG_ADDR(instanceIdChBelongto + 1U), TMR_STS_UIFLG_MASK);
    /* get channel id offset value */
    chModOffset = ((Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM * (Pwm_TmrChIdType)instanceIdChBelongto) + hwChannelId;
    /* Clear notification bit flag for current channel*/
    s_NotifToChannelMap[chModOffset] &= (uint8)(~(uint32)(PWM_TMR_CCXIFLG_EDGE|PWM_TMR_UIFLG_EDGE));

    if(PWM_BOTH_EDGES == Notification)
    {
        s_NotifToChannelMap[chModOffset] |= PWM_TMR_UIFLG_EDGE | PWM_TMR_CCXIFLG_EDGE;
    }
    else if(PWM_RISING_EDGE == Notification)
    {
        edgeCal = (Pwm_TmrNotifyConditionType)((PWM_HIGH == chPolarity) ? PWM_TMR_CCXIFLG_EDGE : PWM_TMR_UIFLG_EDGE);
        s_NotifToChannelMap[chModOffset] |= edgeCal;
    }
    else
    {
        edgeCal = (Pwm_TmrNotifyConditionType)((PWM_LOW == chPolarity) ? PWM_TMR_CCXIFLG_EDGE  : PWM_TMR_UIFLG_EDGE);
        s_NotifToChannelMap[chModOffset] |= edgeCal;
    }

    /* If duty cycle is not 0% or 100%*/
    if (((uint16)0U) != (s_ChDutyCycle[ChannelNumber] & (uint16)PWM_TMR_DUTY_CYCLE_MASK_VAL))
    {
        /* if UIEN is needed */
        if(PWM_TMR_UIFLG_EDGE == (s_NotifToChannelMap[chModOffset] & PWM_TMR_UIFLG_EDGE))
        {
            /* Enable UIEN interrupt */
            REG_BIT_SET32(TMR_DIEN_REG_ADDR(instanceIdChBelongto + 1U), TMR_DIEN_UIEN_MASK);
        }
        else
        {
            /* do nothing */
        }

        if(PWM_TMR_CCXIFLG_EDGE == (s_NotifToChannelMap[chModOffset] & PWM_TMR_CCXIFLG_EDGE))
        {
            
            /* Clear flag */
            REG_BIT_CLEAR32(TMR_STS_REG_ADDR(instanceIdChBelongto + 1U), (uint32)1U << (hwChannelId + 1U));
            /* Enable interrupts */
            REG_BIT_SET32(TMR_DIEN_REG_ADDR(instanceIdChBelongto + 1U), (uint32)1U << (hwChannelId + 1U));
        }
        else
        {
            /* Disable interrupts */
            REG_BIT_CLEAR32(TMR_DIEN_REG_ADDR(instanceIdChBelongto + 1U), (uint32)1U << (hwChannelId + 1U));
        }
    }
    else
    {
        /* disable match compare interrupt */
        Pwm_Tmr_DisableCmpInterruptIrq(instanceIdChBelongto, hwChannelId);
        s_NotifToChannelMap[chModOffset] |= PWM_TMR_UIFLG_NO_EDGE_NOTIF;
    }
    SchM_Exit_Pwm_PWM_CRITICAL_SECTION4();
}
#endif

#if (STD_ON == PWM_LOW_POWER_STATE_ENABLE)
/*!
* @brief         CheckChIdleState function of the pwm TMR Low-level driver.
*
* @param[in]     None
* @param[out]    None
* @param[in,out] None
*
* @retval        Std_ReturnType:E_OK/E_NOT_OK
*/
FUNC(Std_ReturnType, PWM_CODE) Pwm_Tmr_CheckChIdleState(void)
{
    /* channel id, used for count */
    VAR(Pwm_TmrChIdType, AUTOMATIC) count = (Pwm_TmrChIdType)0;
    /* save check resrlt */
    VAR(Std_ReturnType, AUTOMATIC) returnValue = (Std_ReturnType)E_OK;

    for(count = (uint8)0; count < (uint8)PWM_TMR_CHANNELS_NUM; count++)
    {
        if((uint8)PWM_TMR_CHANNEL_IS_RUNNING == s_ChState[count])
        {
            returnValue = (Std_ReturnType)E_NOT_OK;
            break;
        }
        else
        {
            /* do nothing */
        }
    }

    return returnValue;
}

/*!
* @brief         SetPowerState function of the pwm TMR Low-level driver.
*
* @param[in]     pTmrIpCfgPtr         - pointer to the tmr channel configuration
* @param[in]     TargetPowerState     - target power state
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC(void, PWM_CODE) Pwm_Tmr_SetPowerState(P2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr,
                                               VAR(Pwm_PowerStateType, AUTOMATIC) TargetPowerState)
{
    /* used for count */
    VAR(uint8, AUTOMATIC) count = 0U;
    /* Pointer to Tmr register struct */
    P2CONST(Pwm_TmrRegValType, AUTOMATIC, PWM_APPL_CONST) pRegValPtr = NULL_PTR;
    /* tmr hardware instance id */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) hwInstanceId = (uint8)0U;

    for(count = 0U; count < (pTmrIpCfgPtr->cfgTmrNumber); count++)
    {
        /* Get pointer to Tmr register struct */
        pRegValPtr = &(*pTmrIpCfgPtr->pCfgTmrPtr)[count];
        /* Get tmr hardware instance id */
        hwInstanceId = pRegValPtr->tmrName;

        if(PWM_LOW_POWER == TargetPowerState)
        {
            if(PWM_TMR1 == hwInstanceId)
            {
                Mcu_Rcm_OperationPeriphClock(DISABLE, RCM_APB2_PERIPH, (uint32)RCM_APB2_PERIPH_TMR1);
            }
            else if(PWM_TMR2 == hwInstanceId)
            {
                Mcu_Rcm_OperationPeriphClock(DISABLE, RCM_APB1_PERIPH, (uint32)RCM_APB1_PERIPH_TMR2);
            }
            else if(PWM_TMR3 == hwInstanceId)
            {
                Mcu_Rcm_OperationPeriphClock(DISABLE, RCM_APB1_PERIPH, (uint32)RCM_APB1_PERIPH_TMR3);
            }
            else
            {
                Mcu_Rcm_OperationPeriphClock(DISABLE, RCM_APB1_PERIPH, (uint32)RCM_APB1_PERIPH_TMR4);
            }
        }
        else
        {
            if(PWM_TMR1 == hwInstanceId)
            {
                Mcu_Rcm_OperationPeriphClock(ENABLE, RCM_APB2_PERIPH, (uint32)RCM_APB2_PERIPH_TMR1);
            }
            else if(PWM_TMR2 == hwInstanceId)
            {
                Mcu_Rcm_OperationPeriphClock(ENABLE, RCM_APB1_PERIPH, (uint32)RCM_APB1_PERIPH_TMR2);
            }
            else if(PWM_TMR3 == hwInstanceId)
            {
                Mcu_Rcm_OperationPeriphClock(ENABLE, RCM_APB1_PERIPH, (uint32)RCM_APB1_PERIPH_TMR3);
            }
            else
            {
                Mcu_Rcm_OperationPeriphClock(ENABLE, RCM_APB1_PERIPH, (uint32)RCM_APB1_PERIPH_TMR4);
            }
        }
    }
}
#endif

#if (STD_ON == PWM_DUAL_CLOCK_MODE_SUPPORTED)
/*!
* @brief         SetClkPrescaler function of the pwm TMR Low-level driver.
*
* @param[in]     ClkPscMode        - prescaler mode
* @param[in]     pTmrIpCfgPtr      - pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_SetClkPrescaler(VAR(Pwm_ClockDivisionType, AUTOMATIC) ClkPscMode,
                      CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* used for count */
    VAR(uint8, AUTOMATIC) count = 0U;
    /* tmr hardware instance id */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) hwInstanceId = (uint8)0U;
    /* Pointer to Tmr register struct */
    P2CONST(Pwm_TmrRegValType, AUTOMATIC, PWM_APPL_CONST) pRegValPtr = NULL_PTR;

    SchM_Enter_Pwm_PWM_CRITICAL_SECTION7();

    for (count = 0U; count < (pTmrIpCfgPtr->cfgTmrNumber); count++)
    {
        pRegValPtr = &(*pTmrIpCfgPtr->pCfgTmrPtr)[count];
        hwInstanceId = pRegValPtr->tmrName;

        if(PWM_CLK_DIV_ALTERNATE == ClkPscMode)
        {
            REG_WRITE32(TMR_PSC_REG_ADDR(hwInstanceId + 1U), pRegValPtr->pscAlt);
        }
        else
        {
            REG_WRITE32(TMR_PSC_REG_ADDR(hwInstanceId + 1U), pRegValPtr->tmrPsc);
        }
    }

    SchM_Exit_Pwm_PWM_CRITICAL_SECTION7();
}
#endif

#if (STD_ON == PWM_SET_OUTPUT_TO_ACTIVE)
/*!
* @brief         SetOutputToActive function of the pwm TMR Low-level driver.
*
* @param[in]     ChannelNumber      - channel id
* @param[in]     pTmrIpCfgPtr       - pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_SetOutputToActive(VAR(uint8, AUTOMATIC) ChannelNumber,
                      CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* Get pointer to Tmr channel configuration struct */
    P2CONST(Pwm_TmrChCfgType, AUTOMATIC, PWM_APPL_CONST) pChCfgPtr = &(*pTmrIpCfgPtr->pCfgChPtr)[ChannelNumber];
    /* get hardware channel Id */
    VAR(Pwm_TmrChIdType, AUTOMATIC) hwChannelId = ((pChCfgPtr->pwmChName) & PWM_TMR_CHANNEL_MASK_BITS);
    /* get tmr instance id that channel belongs to */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) instanceIdChBelongto = (uint8)
                                         (((pChCfgPtr->pwmChName) & PWM_TMR_MODULE_MASK_BITS) >> PWM_TMR_MODULE_SHIFT_VAL);

    SchM_Enter_Pwm_PWM_CRITICAL_SECTION5();
    if ((uint8)PWM_TMR_CHANNEL_IS_RUNNING == s_ChState[ChannelNumber])
    {
#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
        /* Disable match compare interrupt */
        Pwm_Tmr_DisableCmpInterruptIrq(instanceIdChBelongto, hwChannelId);
#endif
        /* Set channel to idle state */
        if(PWM_HIGH == pChCfgPtr->pwmChPolarity)
        {
            if((0U == hwChannelId) || (1U == hwChannelId))
            {
                REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * hwChannelId) + 0x04U));
                REG_BIT_SET32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_HIGH_LEVEL << ((0x08U * hwChannelId) + 0x04U));
            }
            else
            {
                REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
                REG_BIT_SET32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_HIGH_LEVEL << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
            }
        }
        else
        {
            if((0U == hwChannelId) || (1U == hwChannelId))
            {
                REG_BIT_CLEAR32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * hwChannelId) + 0x04U));
                REG_BIT_SET32(TMR_CCM1_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_LOW_LEVEL << ((0x08U * hwChannelId) + 0x04U));
            }
            else
            {
                REG_BIT_CLEAR32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_MODE2 << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
                REG_BIT_SET32(TMR_CCM2_REG_ADDR(instanceIdChBelongto + 1U), (uint32)PWM_OUTPUT_LOW_LEVEL << ((0x08U * (uint8)(hwChannelId - 2U)) + 0x04U));
            }
        }
        s_ChState[ChannelNumber] = (uint8)PWM_TMR_CHANNEL_IS_RUNNING;
#if ((STD_ON == PWM_GET_CHANNEL_DUTYCYCLE) || (STD_ON == PWM_NOTIFICATION_SUPPORTED))
        s_ChDutyCycle[ChannelNumber] = (uint16)PWM_TMR_DUTY_CYCLE_FULL;
#endif
    }
    else
    {
        /* do nothing */
    }
    SchM_Exit_Pwm_PWM_CRITICAL_SECTION5();
}
#endif

#if (STD_ON == PWM_SOFTWARE_RESET_COUNTER)
/*!
* @brief         SoftwareResetCounter function of the pwm TMR Low-level driver.
*
* @param[in]     InstanceId      - instance id
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC (void, PWM_CODE) Pwm_Tmr_SoftwareResetCounter(VAR(uint8, AUTOMATIC) InstanceId)
{
    REG_RMW32(TMR_CEG_REG_ADDR(InstanceId + 1U), TMR_CEG_UEG_MASK, TMR_CEG_UEG_MASK);
}
#endif

#if (STD_ON == PWM_GET_CHANNEL_DUTYCYCLE)
/*!
* @brief         GetChDutyCycleValue function of the pwm TMR Low-level driver.
*
* @param[in]     ChannelNumber         - channel id
* @param[out]    None
* @param[in,out] None
*
* @retval        uint16 : channel duty cycle value
*/
FUNC(uint16, PWM_CODE) Pwm_Tmr_GetChDutyCycleValue(VAR(uint8, AUTOMATIC) ChannelNumber)
{
    return (s_ChDutyCycle[ChannelNumber]);
}
#endif

#if (STD_ON == PWM_TURN_ON_OFF_CHANNEL)
/*!
* @brief         Turn on/off pwm channel output Low-level driver.
*
* @param[in]     ChannelNumber        - channel id
* @param[in]     operaFlag            - -TRUE-turn on, FALSE-turn off
* @param[in]     pTmrIpCfgPtr         - pointer to the tmr channel configuration
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC(void, PWM_CODE) Pwm_Tmr_TurnOnOffChannel
                    (VAR(uint8, AUTOMATIC) ChannelNumber, VAR(boolean, AUTOMATIC) operaFlag,
                     CONSTP2CONST(Pwm_TmrIpCfgType, AUTOMATIC, PWM_APPL_CONST) pTmrIpCfgPtr)
{
    /* Get pointer to Tmr channel configuration struct */
    P2CONST(Pwm_TmrChCfgType, AUTOMATIC, PWM_APPL_CONST) pChCfgPtr = &(*pTmrIpCfgPtr->pCfgChPtr)[ChannelNumber];
    /* get hardware channel Id */
    VAR(Pwm_TmrChIdType, AUTOMATIC) hwChannelId = ((pChCfgPtr->pwmChName) & PWM_TMR_CHANNEL_MASK_BITS);
    /* get tmr instance id that channel belongs to */
    VAR(Pwm_TmrInstanceType, AUTOMATIC) instanceIdChBelongto = (uint8)
                                         (((pChCfgPtr->pwmChName) & PWM_TMR_MODULE_MASK_BITS) >> PWM_TMR_MODULE_SHIFT_VAL);

    SchM_Enter_Pwm_PWM_CRITICAL_SECTION8();

    if(operaFlag == TRUE)
    {
        if((pChCfgPtr->pwmChAlign != PWM_EDGE_ALIGN) && (pChCfgPtr->pwmChAlign != PWM_CENTER_ALIGN))
        {
            REG_BIT_SET32(TMR_CCEN_REG_ADDR(instanceIdChBelongto + 1U), ((uint32)0x5U) << (hwChannelId * 4U));
        }
        else
        {
            REG_BIT_SET32(TMR_CCEN_REG_ADDR(instanceIdChBelongto + 1U), ((uint32)0x1U) << (hwChannelId * 4U));
        }
#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
        /** Enable ovf interrupt */
        if(PWM_TMR_INT_CONDITION_NO_EDGE !=
        ((s_NotifToChannelMap[((Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM * instanceIdChBelongto) + hwChannelId])
         & PWM_TMR_UIFLG_EDGE))
        {
           REG_BIT_SET32(TMR_DIEN_REG_ADDR(instanceIdChBelongto + 1U), TMR_DIEN_UIEN_MASK);
        }
        else
        {
            /* do nothing */
        }

        /** Enable match compare interrupt */
        if(PWM_TMR_INT_CONDITION_NO_EDGE !=
        ((s_NotifToChannelMap[((Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM * instanceIdChBelongto) + hwChannelId])
         & PWM_TMR_CCXIFLG_EDGE))
        {
            REG_BIT_SET32(TMR_DIEN_REG_ADDR(instanceIdChBelongto + 1U), 1U << (hwChannelId + 1U));
        }
        else
        {
            /* do nothing */
        }
#endif
    }
    else
    {
        if((pChCfgPtr->pwmChAlign != PWM_EDGE_ALIGN) && (pChCfgPtr->pwmChAlign != PWM_CENTER_ALIGN))
        {
            REG_BIT_CLEAR32(TMR_CCEN_REG_ADDR(instanceIdChBelongto + 1U), ((uint32)0x5U) << (hwChannelId * 4U));
        }
        else
        {
            REG_BIT_CLEAR32(TMR_CCEN_REG_ADDR(instanceIdChBelongto + 1U), ((uint32)0x1U) << (hwChannelId * 4U));
        }
#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
        /** Enable ovf interrupt */
        if(PWM_TMR_INT_CONDITION_NO_EDGE !=
        ((s_NotifToChannelMap[((Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM * instanceIdChBelongto) + hwChannelId])
         & PWM_TMR_UIFLG_EDGE))
        {
           REG_BIT_CLEAR32(TMR_DIEN_REG_ADDR(instanceIdChBelongto + 1U), TMR_DIEN_UIEN_MASK);
        }
        else
        {
            /* do nothing */
        }

        /** Enable match compare interrupt */
        if(PWM_TMR_INT_CONDITION_NO_EDGE !=
        ((s_NotifToChannelMap[((Pwm_TmrChIdType)PWM_PERTMR_CHANNEL_NUM * instanceIdChBelongto) + hwChannelId])
         & PWM_TMR_CCXIFLG_EDGE))
        {
            REG_BIT_CLEAR32(TMR_DIEN_REG_ADDR(instanceIdChBelongto + 1U), 1U << (hwChannelId + 1U));
        }
        else
        {
            /* do nothing */
        }
#endif
    }

    SchM_Exit_Pwm_PWM_CRITICAL_SECTION8();
}
#endif

#if ((STD_ON == PWM_NOTIFICATION_SUPPORTED) || (STD_ON == PWM_OVERFLOW_CHECK_SUPPORTED))
/*!
* @brief         ProcessCommonInterrupt function of the pwm TMR Low-level driver.
*
* @param[in]     TmrModule         - pwm tmr id
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC(void,PWM_CODE) Pwm_Tmr_ProcessCommonInterrupt(CONST(uint8, AUTOMATIC) TmrModule)
{
    VAR(uint32, AUTOMATIC) tmrIntFlag = 0U;
    VAR(uint32, AUTOMATIC) tmrIntEnSts = 0U;
    #if (STD_ON == PWM_OVERFLOW_CHECK_SUPPORTED)
    P2CONST(Pwm_IpCfgType, AUTOMATIC, PWM_APPL_CONST) pIpCfgPtr = Pwm_GetIpCfgPtr();
    uint8 tmrIdx = 0U;
#endif

    /* Get the interrupt flags  */
    tmrIntFlag = REG_READ32(TMR_STS_REG_ADDR(TmrModule + 1U));
    /* Get the interrupt enable status */
    tmrIntEnSts = REG_READ32(TMR_DIEN_REG_ADDR(TmrModule + 1U));

    /* Check the overflow bit */
    if(0U == (tmrIntFlag & TMR_STS_UIFLG_MASK))
    {
        /* nothing to do */
    }
    else if(0U == (tmrIntEnSts & TMR_DIEN_UIEN_MASK))
    {
        /* nothing to do */
    }
    else if(TmrModule == PWM_TMR1)
    {
        /* nothing to do */
    }
    else
    {
    #if (STD_ON == PWM_OVERFLOW_CHECK_SUPPORTED)
        for(tmrIdx = 0U; tmrIdx < pIpCfgPtr->pTmrIpCfgPtr->cfgTmrNumber; tmrIdx++)
        {
            if((*(pIpCfgPtr->pTmrIpCfgPtr->pCfgTmrPtr))[tmrIdx].tmrName == TmrModule)
            {
                (*(pIpCfgPtr->pTmrIpCfgPtr->pCfgTmrPtr))[tmrIdx].pwmTmrOverflowNotifyPtr(TmrModule);
                break;
            }
            else
            {
                /* do nothing */
            }
        }
    #endif

        /* clear the channel update flag */
        REG_BIT_CLEAR32(TMR_STS_REG_ADDR(TmrModule + 1U), TMR_STS_UIFLG_MASK);
    }

#if (STD_ON == PWM_NOTIFICATION_SUPPORTED)
    /* Channel 1 interrupt */
    if(0U == (tmrIntFlag & TMR_STS_CC1IFLG_MASK))
    {
        /* nothing to do */
    }
    else if(0U == (tmrIntEnSts & TMR_DIEN_CC1IEN_MASK))
    {
        /* nothing to do */
    }
    else
    {
        Pwm_Tmr_InvokeNotification(PWM_TMR_CH1, TmrModule);
    }

    /* Channel 2 interrupt */
    if(0U == (tmrIntFlag & TMR_STS_CC2IFLG_MASK))
    {
        /* nothing to do */
    }
    else if(0U == (tmrIntEnSts & TMR_DIEN_CC2IEN_MASK))
    {
        /* nothing to do */
    }
    else
    {
        Pwm_Tmr_InvokeNotification(PWM_TMR_CH2, TmrModule);
    }

    /* Channel 3 interrupt */
    if(0U == (tmrIntFlag & TMR_STS_CC3IFLG_MASK))
    {
        /* nothing to do */
    }
    else if(0U == (tmrIntEnSts & TMR_DIEN_CC3IEN_MASK))
    {
        /* nothing to do */
    }
    else
    {
        Pwm_Tmr_InvokeNotification(PWM_TMR_CH3, TmrModule);
    }

    /* Channel 4 interrupt */
    if(0U == (tmrIntFlag & TMR_STS_CC4IFLG_MASK))
    {
        /* nothing to do */
    }
    else if(0U == (tmrIntEnSts & TMR_DIEN_CC4IEN_MASK))
    {
        /* nothing to do */
    }
    else
    {
        Pwm_Tmr_InvokeNotification(PWM_TMR_CH4, TmrModule);
    }
#endif
}
#endif

#if ((STD_ON == PWM_OVERFLOW_CHECK_SUPPORTED) || (STD_ON == PWM_FAULT_CHECK_SUPPORTED))
/*!
* @brief         ProcessTofAndFaultInterrupt function of the pwm TMR Low-level driver.
*
* @param[in]     TmrModule         - pwm tmr instance id
* @param[out]    None
* @param[in,out] None
*
* @retval        None
*/
FUNC(void,PWM_CODE) Pwm_Tmr1_ProcessTofAndFaultInterrupt(CONST (uint8, AUTOMATIC) TmrModule)
{
    VAR(uint32, AUTOMATIC) tmrIntFlag = 0U;
    VAR(uint32, AUTOMATIC) tmrIntEnSts = 0U;
#if (STD_ON == PWM_FAULT_CHECK_SUPPORTED) || (STD_ON == PWM_OVERFLOW_CHECK_SUPPORTED)
    P2CONST(Pwm_IpCfgType, AUTOMATIC, PWM_APPL_CONST) pIpCfgPtr = Pwm_GetIpCfgPtr();
    uint8 tmrIdx = 0U;
#endif

    /* Get the interrupt flags  */
    tmrIntFlag = REG_READ32(TMR_STS_REG_ADDR(TmrModule + 1U));
    /* Get the interrupt enable status */
    tmrIntEnSts = REG_READ32(TMR_DIEN_REG_ADDR(TmrModule + 1U));

    /* Check the overflow bit */
    if(0U == (tmrIntFlag & TMR_STS_UIFLG_MASK))
    {
        /* nothing to do */
    }
    else if(0U == (tmrIntEnSts & TMR_DIEN_UIEN_MASK))
    {
        /* nothing to do */
    }
    else
    {
    #if (STD_ON == PWM_OVERFLOW_CHECK_SUPPORTED)
        for(tmrIdx = 0U; tmrIdx < pIpCfgPtr->pTmrIpCfgPtr->cfgTmrNumber; tmrIdx++)
        {
            if((*(pIpCfgPtr->pTmrIpCfgPtr->pCfgTmrPtr))[tmrIdx].tmrName == TmrModule)
            {
                (*(pIpCfgPtr->pTmrIpCfgPtr->pCfgTmrPtr))[tmrIdx].pwmTmrOverflowNotifyPtr(TmrModule);
                break;
            }
            else
            {
                /* do nothing */
            }
        }
    #endif

        /* clear the channel update flag */
        REG_BIT_CLEAR32(TMR_STS_REG_ADDR(TmrModule + 1U), TMR_STS_UIFLG_MASK);
    }

    /* Check the BRK flag */
    if(0U == (tmrIntFlag & TMR_STS_BRKIFLG_MASK))
    {
        /* nothing to do */
    }
    else if(0U == (tmrIntEnSts & TMR_DIEN_BRKIEN_MASK))
    {
        /* nothing to do */
    }
    else
    {
    #if (STD_ON == PWM_FAULT_CHECK_SUPPORTED)
        for(tmrIdx = 0U; tmrIdx < pIpCfgPtr->pTmrIpCfgPtr->cfgTmrNumber; tmrIdx++)
        {
            if((*(pIpCfgPtr->pTmrIpCfgPtr->pCfgTmrPtr))[tmrIdx].tmrName == TmrModule)
            {
                (*(pIpCfgPtr->pTmrIpCfgPtr->pCfgTmrPtr))[tmrIdx].pwmTmrFaultNotifyPtr(TmrModule);
                break;
            }
            else
            {
                /* do nothing */
            }
        }
    #endif

        /* clear the break flag */
        REG_BIT_CLEAR32(TMR_STS_REG_ADDR(TmrModule + 1U), TMR_STS_BRKIFLG_MASK);
    }
}
#endif

/**@} end of group PWM_Fuctions */

#define PWM_STOP_SEC_CODE
#include "Pwm_MemMap.h"

#ifdef __cplusplus
}
#endif

/**@} end of group PWM_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
