/*!
* @file     Port_Reg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the port module.
*
* @details  This header file includes the register definitions of the port module.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef PORT_REG_H
#define PORT_REG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup PORT_Driver
  @{
*/

/** @defgroup PORT_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
***********************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define PORT_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define PORT_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PORT_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PORT_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define PORT_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PORT_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PORT_REG_H_SW_PATCH_VERSION                        0x00U

/**@} end of group PORT_Macros */
/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
***********************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Port_Reg.h and Reg_eSys.h */
    #if (PORT_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Port_Reg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Port_Reg.h and Reg_eSys.h */
    #if (PORT_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Port_Reg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
                                             GLOBAL VARIABLE
***********************************************************************************************************/
#define PORT_START_SEC_CONST_32
#include "Port_MemMap.h"

/** @defgroup PORT_Variable
  @{
*/

/** The declaration of the port base address array  */
extern CONST(uint32, PORT_CONST) PORT_BASEADDR_ARR[6];

/**@} end of group PORT_Variable */

#define PORT_STOP_SEC_CONST_32
#include "Port_MemMap.h"
/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_MODE
************************************************************************************************************/
/** @defgroup PORT_Driver
  @{
*/

/** @defgroup PORT_Macros
  @{
*/

/** GPIOx_MODE register address */
/** Note: The value of PORT can be 0, 1, 2, 3, 5. */
#define GPIO_MODE_REG_ADDR(PORT)         ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x00U))

#define GPIO_MODE_MASK                   ((uint32)0xFFFFFFFFU)
#define GPIO_MODE_SHIFT                  ((uint8)0U)

/** Note: The value of PIN can be 0 ~ 15. */
#define GPIO_INPUT_STATE(PIN)            ((uint32)(0U << (PIN * 2U)))
#define GPIO_OUTPUT_STATE(PIN)           ((uint32)(1U << (PIN * 2U)))
#define GPIO_AF_STATE(PIN)               ((uint32)(2U << (PIN * 2U)))
#define GPIO_ANALOG_STATE(PIN)           ((uint32)(3U << (PIN * 2U)))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_OMODE
************************************************************************************************************/
/** GPIOx_OMODE register address */
/** Note: The value of PORT can be 0, 1, 2, 3, 5. */
#define GPIO_OMODE_REG_ADDR(PORT)        ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x04U))

#define GPIO_OMODE_MASK                  ((uint32)0x0000FFFFU)
#define GPIO_OMODE_SHIFT                 ((uint8)0U)

/** Note: The value of PIN can be 0 ~ 15. */
#define GPIO_PIN_PP_STATE(PIN)           ((uint32)(0U << PIN))
#define GPIO_PIN_OD_STATE(PIN)           ((uint32)(1U << PIN))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_OSSEL
************************************************************************************************************/
/** GPIOx_OSSEL register address */
/** Note: The value of PORT can be 0, 1, 2, 3, 5. */
#define GPIO_OSSEL_REG_ADDR(PORT)        ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x08U))

#define GPIO_OSSEL_MASK                  ((uint32)0xFFFFFFFFU)
#define GPIO_OSSEL_SHIFT                 ((uint8)0U)

/** Note: The value of PIN can be 0 ~ 15. */
#define GPIO_LOW_SPEED(PIN)              ((uint32)(0U << (PIN * 2U)))
#define GPIO_MEDIUM_SPEED(PIN)           ((uint32)(1U << (PIN * 2U)))
#define GPIO_HIGH_SPEED(PIN)             ((uint32)(3U << (PIN * 2U)))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_PUPD
************************************************************************************************************/
/** GPIOx_PUPD register address */
/** Note: The value of PORT can be 0, 1, 2, 3, 5. */
#define GPIO_PUPD_REG_ADDR(PORT)         ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x0CU))

#define GPIO_PUPD_MASK                   ((uint32)0xFFFFFFFFU)
#define GPIO_PUPD_SHIFT                  ((uint8)0U)

/** Note: The value of PIN can be 0 ~ 15. */
#define GPIO_NO_PULL(PIN)                ((uint32)(0U << (PIN * 2U)))
#define GPIO_PULL_UP(PIN)                ((uint32)(1U << (PIN * 2U)))
#define GPIO_PULL_DOWN(PIN)              ((uint32)(2U << (PIN * 2U)))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_LOCK
************************************************************************************************************/
/** GPIOx_LOCK register address */
/** Note: The value of PORT can be 0, 1. */
#define GPIO_LOCK_REG_ADDR(PORT)         ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x1CU))

#define GPIO_LOCK_LOCK_MASK              ((uint32)0x0000FFFFU)
#define GPIO_LOCK_LOCK_SHIFT             ((uint8)0U)

#define GPIO_LOCK_LOCKKEY_MASK           ((uint32)0x00010000U)
#define GPIO_LOCK_LOCKKEY_SHIFT          ((uint8)16U)

/** Note: The value of PIN can be 0 ~ 15. */
#define GPIO_PIN_LOCK(PIN)               ((uint32)(1U << PIN))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_ALFL
************************************************************************************************************/
/** GPIOx_ALFL register address */
/** Note: The value of PORT can be 0, 1, 2, 3, 5. */
#define GPIO_ALFL_REG_ADDR(PORT)         ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x20U))

#define GPIO_ALFL_MASK                   ((uint32)0xFFFFFFFFU)
#define GPIO_ALFL_SHIFT                  ((uint8)0U)

/** Note: The value of PIN can be 0 ~ 7. */
/** Note: The value of TYPE can be 0 ~ 7. */
#define GPIO_LOW_PIN_AF(PIN, TYPE)       ((uint32)(TYPE << (PIN * 4U)))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_ALFH
************************************************************************************************************/
/** GPIOx_ALFH register address */
/** Note: The value of PORT can be 0, 1, 2, 3, 5. */
#define GPIO_ALFH_REG_ADDR(PORT)         ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x24U))

#define GPIO_ALFH_MASK                   ((uint32)0xFFFFFFFFU)
#define GPIO_ALFH_SHIFT                  ((uint8)0U)

/** Note: The value of PIN can be 8 ~ 15. */
/** Note: The value of TYPE can be 0 ~ 7. */
#define GPIO_HIGH_PIN_AF(PIN, TYPE)      ((uint32)(TYPE << ((PIN - 8) * 4)))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_FILTER_EN
************************************************************************************************************/
/** GPIOx_FILTER_EN register address */
/** Note: The value of PORT can be 0, 1, 2, 3, 5. */
#define GPIO_FILTER_EN_REG_ADDR(PORT)    ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x30U))

#define GPIO_FILTER_EN_MASK              ((uint32)0x0000FFFFU)
#define GPIO_FILTER_EN_SHIFT             ((uint8)0U)

/** Note: The value of PIN can be 0 ~ 15. */
#define GPIO_PIN_FILTER_EN(PIN)          ((uint32)((uint32)1U << (uint32)PIN))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_BSC
***********************************************************************************************************/
/** GPIOx_BSC register address */
/** Note: The value of PORT can be 0, 1, 2, 3, 5. */
#define GPIO_BSC_REG_ADDR(PORT)          ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x18U))

#define GPIO_BSC_BS_MASK                 ((uint32)0x0000FFFFU)
#define GPIO_BSC_BS_SHIFT                ((uint8)0U)

#define GPIO_BSC_BC_MASK                 ((uint32)0xFFFF0000U)
#define GPIO_BSC_BC_SHIFT                ((uint8)16U)

/** Note: The value of PIN can be 0 ~ 15. */
#define GPIO_BSC_SET_PIN_LEVEL(PIN)      ((uint32)(1U << PIN))
#define GPIO_BSC_RESET_PIN_LEVEL(PIN)    ((uint32)(1U << (PIN + GPIO_BSC_BC_SHIFT)))

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: GPIOx_BR
***********************************************************************************************************/
/** GPIOx_BSC register address */
/** Note: The value of PORT can be 0, 1, 2, 3, 5. */
#define GPIO_BR_REG_ADDR(PORT)          ((uint32)(PORT_BASEADDR_ARR[PORT] + (uint32)0x28U))

#define GPIO_BR_MASK                    ((uint32)0x0000FFFFU)
#define GPIO_BR_SHIFT                   ((uint8)0U)

/** Note: The value of PIN can be 0 ~ 15. */
#define GPIO_BR_RESET_PIN_LEVEL(PIN)    ((uint32)(1U << PIN))

/**@} end of group PORT_Macros */

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* PORT_REG_H */

/**@} end of group PORT_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
