/*!
* @file     Rtc_Reg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the RTC module.
*           This header file includes the register definitions of the RTC module.
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_15-Nov-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef RTC_REG_H
#define RTC_REG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"
/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup RTC_Driver
  * @brief RTC driver modules
  @{
*/

/** @defgroup RTC_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define RTC_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define RTC_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define RTC_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define RTC_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define RTC_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define RTC_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define RTC_REG_H_SW_PATCH_VERSION                        0x00U

/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Rtc_Reg.h and Reg_eSys.h */
    #if (RTC_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Rtc_Reg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Rtc_Reg.h and Reg_eSys.h */
    #if (RTC_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Rtc_Reg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
                                            MACRO DEFINITION
************************************************************************************************************/

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_TIME (Base + 0x00)
************************************************************************************************************/
/** RTC_TIME register address */
#define RTC_TIME_REG_ADDR                   ((uint32)(RTC_BASEADDR + (uint32)0U))

#define RTC_TIME_SECU_MASK                  ((uint32)0x0000000FU)
#define RTC_TIME_SECU_SHIFT                 ((uint8)0U)

#define RTC_TIME_SECT_MASK                  ((uint32)0x00000070U)
#define RTC_TIME_SECT_SHIFT                 ((uint8)4U)

#define RTC_TIME_MINU_MASK                  ((uint32)0x00000F00U)
#define RTC_TIME_MINU_SHIFT                 ((uint8)8U)

#define RTC_TIME_MINT_MASK                  ((uint32)0x00007000U)
#define RTC_TIME_MINT_SHIFT                 ((uint8)12U)

#define RTC_TIME_HRU_MASK                   ((uint32)0x000F0000U)
#define RTC_TIME_HRU_SHIFT                  ((uint8)16U)

#define RTC_TIME_HRT_MASK                   ((uint32)0x00300000U)
#define RTC_TIME_HRT_SHIFT                  ((uint8)20U)

#define RTC_TIME_TIMEFCFG_MASK              ((uint32)0x00400000U)
#define RTC_TIME_TIMEFCFG_SHIFT             ((uint8)22U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_DATE (Base + 0x04)
************************************************************************************************************/
/** RTC_DATE register address */
#define RTC_DATE_REG_ADDR                   ((uint32)(RTC_BASEADDR + (uint32)0x04U))

#define RTC_DATE_DAYU_MASK                  ((uint32)0x0000000FU)
#define RTC_DATE_DAYU_SHIFT                 ((uint8)0U)

#define RTC_DATE_DAYT_MASK                  ((uint32)0x00000030U)
#define RTC_DATE_DAYT_SHIFT                 ((uint8)4U)

#define RTC_DATE_MONU_MASK                  ((uint32)0x00000F00U)
#define RTC_DATE_MONU_SHIFT                 ((uint8)8U)

#define RTC_DATE_MONT_MASK                  ((uint32)0x00001000U)
#define RTC_DATE_MONT_SHIFT                 ((uint8)12U)

#define RTC_DATE_WEEKSEL_MASK               ((uint32)0x0000E000U)
#define RTC_DATE_WEEKSEL_SHIFT              ((uint8)13U)

#define RTC_DATE_YRU_MASK                   ((uint32)0x000F0000U)
#define RTC_DATE_YRU_SHIFT                  ((uint8)16U)

#define RTC_DATE_YRT_MASK                   ((uint32)0x00F00000U)
#define RTC_DATE_YRT_SHIFT                  ((uint8)20U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_CTRL (Base + 0x08)
************************************************************************************************************/
/** RTC_CTRL register address */
#define RTC_CTRL_REG_ADDR                   ((uint32)(RTC_BASEADDR + (uint32)0x08U))

#define RTC_CTRL_RCMCFG_MASK                ((uint32)0x00000020U)
#define RTC_CTRL_RCMCFG_SHIFT               ((uint8)5U)

#define RTC_CTRL_TIMEFCFG_MASK              ((uint32)0x00000040U)
#define RTC_CTRL_TIMEFCFG_SHIFT             ((uint8)6U)

#define RTC_CTRL_ALREN_MASK                 ((uint32)0x00000100U)
#define RTC_CTRL_ALREN_SHIFT                ((uint8)8U)

#define RTC_CTRL_ALRIEN_MASK                ((uint32)0x00001000U)
#define RTC_CTRL_ALRIEN_SHIFT               ((uint8)12U)

#define RTC_CTRL_WUTIEN_MASK                ((uint32)0x00004000U)
#define RTC_CTRL_WUTIEN_SHIFT               ((uint8)14U)

#define RTC_CTRL_STCCFG_MASK                ((uint32)0x00010000U)
#define RTC_CTRL_STCCFG_SHIFT               ((uint8)16U)

#define RTC_CTRL_WTCCFG_MASK                ((uint32)0x00020000U)
#define RTC_CTRL_WTCCFG_SHIFT               ((uint8)17U)

#define RTC_CTRL_BAKE_MASK                  ((uint32)0x00040000U)
#define RTC_CTRL_BAKE_SHIFT                 ((uint8)18U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_STS (Base + 0x0C)
************************************************************************************************************/
/** RTC_STS register address */
#define RTC_STS_REG_ADDR                    ((uint32)(RTC_BASEADDR + (uint32)0x0CU))

#define RTC_STS_ALRWFLG_MASK                ((uint32)0x00000001U)
#define RTC_STS_ALRWFLG_SHIFT               ((uint8)0U)

#define RTC_STS_SOPFLG_MASK                 ((uint32)0x00000008U)
#define RTC_STS_SOPFLG_SHIFT                ((uint8)3U)

#define RTC_STS_INITSFLG_MASK               ((uint32)0x00000010U)
#define RTC_STS_INITSFLG_SHIFT              ((uint8)4U)

#define RTC_STS_RSFLG_MASK                  ((uint32)0x00000020U)
#define RTC_STS_RSFLG_SHIFT                 ((uint8)5U)

#define RTC_STS_RINITFLG_MASK               ((uint32)0x00000040U)
#define RTC_STS_RINITFLG_SHIFT              ((uint8)6U)

#define RTC_STS_INITEN_MASK                 ((uint32)0x00000080U)
#define RTC_STS_INITEN_SHIFT                ((uint8)7U)

#define RTC_STS_ALRAFLG_MASK                ((uint32)0x00000100U)
#define RTC_STS_ALRAFLG_SHIFT               ((uint8)8U)

#define RTC_STS_RCALPFLG_MASK               ((uint32)0x00010000U)
#define RTC_STS_RCALPFLG_SHIFT              ((uint8)16U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_PSC (Base + 0x10)
************************************************************************************************************/
/** RTC_PSC register address */
#define RTC_PSC_REG_ADDR                    ((uint32)(RTC_BASEADDR + (uint32)0x10U))

#define RTC_PSC_SPSC_MASK                   ((uint32)0x00007FFFU)
#define RTC_PSC_SPSC_SHIFT                  ((uint8)0U)

#define RTC_PSC_APSC_MASK                   ((uint32)0x007F0000U)
#define RTC_PSC_APSC_SHIFT                  ((uint8)16U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_ALRMA (Base + 0x1C)
************************************************************************************************************/
/** RTC_ALRMA register address */
#define RTC_ALRMA_REG_ADDR                  ((uint32)(RTC_BASEADDR + (uint32)0x1CU))

#define RTC_ALRMA_SECU_MASK                 ((uint32)0x0000000FU)
#define RTC_ALRMA_SECU_SHIFT                ((uint8)0U)

#define RTC_ALRMA_SECT_MASK                 ((uint32)0x00000070U)
#define RTC_ALRMA_SECT_SHIFT                ((uint8)4U)

#define RTC_ALRMA_SECMEN_MASK               ((uint32)0x00000080U)
#define RTC_ALRMA_SECMEN_SHIFT              ((uint8)7U)

#define RTC_ALRMA_MINU_MASK                 ((uint32)0x00000F00U)
#define RTC_ALRMA_MINU_SHIFT                ((uint8)8U)

#define RTC_ALRMA_MINT_MASK                 ((uint32)0x00007000U)
#define RTC_ALRMA_MINT_SHIFT                ((uint8)12U)

#define RTC_ALRMA_MINMEN_MASK               ((uint32)0x00008000U)
#define RTC_ALRMA_MINMEN_SHIFT              ((uint8)15U)

#define RTC_ALRMA_HRU_MASK                  ((uint32)0x000F0000U)
#define RTC_ALRMA_HRU_SHIFT                 ((uint8)16U)

#define RTC_ALRMA_HRT_MASK                  ((uint32)0x00300000U)
#define RTC_ALRMA_HRT_SHIFT                 ((uint8)20U)

#define RTC_ALRMA_TIMEFCFG_MASK             ((uint32)0x00400000U)
#define RTC_ALRMA_TIMEFCFG_SHIFT            ((uint8)22U)

#define RTC_ALRMA_HRMEN_MASK                ((uint32)0x00800000U)
#define RTC_ALRMA_HRMEN_SHIFT               ((uint8)23U)

#define RTC_ALRMA_DAYU_MASK                 ((uint32)0x0F000000U)
#define RTC_ALRMA_DAYU_SHIFT                ((uint8)24U)

#define RTC_ALRMA_DAYT_MASK                 ((uint32)0x30000000U)
#define RTC_ALRMA_DAYT_SHIFT                ((uint8)28U)

#define RTC_ALRMA_WEEKSEL_MASK              ((uint32)0x40000000U)
#define RTC_ALRMA_WEEKSEL_SHIFT             ((uint8)30U)

#define RTC_ALRMA_DAYEMEN_MASK              ((uint32)0x80000000U)
#define RTC_ALRMA_DAYEMEN_SHIFT             ((uint8)31U)

#define RTC_ALRMA_ALL_MASK                  ((uint32)0x80808080U)
#define RTC_ALRMA_NONE_MASK                 ((uint32)0x00000000U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_WRPROT (Base + 0x24)
************************************************************************************************************/
/** RTC_WRPROT register address */
#define RTC_WRPROT_REG_ADDR                  ((uint32)(RTC_BASEADDR + (uint32)0x24U))

#define RTC_WRPROT_KEY_MASK                  ((uint32)0x0000FFFFU)
#define RTC_WRPROT_KEY_SHIFT                 ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_SUBSEC (Base + 0x28)
************************************************************************************************************/
/** RTC_SUBSEC register address */
#define RTC_SUBSEC_REG_ADDR                  ((uint32)(RTC_BASEADDR + (uint32)0x28U))

#define RTC_SUBSEC_SUBSEC_MASK               ((uint32)0x0000FFFFU)
#define RTC_SUBSEC_SUBSEC_SHIFT              ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_SHIFT (Base + 0x2C)
************************************************************************************************************/
/** RTC_SHIFT register address */
#define RTC_SHIFT_REG_ADDR                  ((uint32)(RTC_BASEADDR + (uint32)0x2CU))

#define RTC_SHIFT_SFSEC_MASK                ((uint32)0x00007FFFU)
#define RTC_SHIFT_SFSEC_SHIFT               ((uint8)0U)

#define RTC_SHIFT_ADD1SECEN_MASK            ((uint32)0x80000000U)
#define RTC_SHIFT_ADD1SECEN_SHIFT           ((uint8)31U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_CAL (Base + 0x3C)
************************************************************************************************************/
/** RTC_CAL register address */
#define RTC_CAL_REG_ADDR                    ((uint32)(RTC_BASEADDR + (uint32)0x3CU))

#define RTC_CAL_RECALF_MASK                 ((uint32)0x000001FFU)
#define RTC_CAL_RECALF_SHIFT                ((uint8)0U)

#define RTC_CAL_CAL16CFG_MASK               ((uint32)0x00002000U)
#define RTC_CAL_CAL16CFG_SHIFT              ((uint8)13U)

#define RTC_CAL_CAL8CFG_MASK                ((uint32)0x00004000U)
#define RTC_CAL_CAL8CFG_SHIFT               ((uint8)14U)

#define RTC_CAL_ICALFEN_MASK                ((uint32)0x00008000U)
#define RTC_CAL_ICALFEN_SHIFT               ((uint8)15U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: RTC_ALRMASS (Base + 0x44)
************************************************************************************************************/
/** RTC_ALRMASS register address */
#define RTC_ALRMASS_REG_ADDR                ((uint32)(RTC_BASEADDR + (uint32)0x44U))

#define RTC_ALRMASS_SUBSEC_MASK             ((uint32)0x00007FFFU)
#define RTC_ALRMASS_SUBSEC_SHIFT            ((uint8)0U)

#define RTC_ALRMASS_MASKSEL_MASK            ((uint32)0x0F000000U)
#define RTC_ALRMASS_MASKSEL_SHIFT           ((uint8)24U)

/**@} end of group RTC_Macros */
#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* RTC_REG_H */
/**@} end of group RTC_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */

