/*!
* @file     Adc_Reg.h
*
* @version  1.0.0
*
* @brief    The header of the register definitions of the ADC module.
*
* @details  This header file includes the register definitions of the ADC module.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef ADC_REG_H
#define ADC_REG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @addtogroup ADC_Driver
  @{
*/

/** @defgroup ADC_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define ADC_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */
#define ADC_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define ADC_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define ADC_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define ADC_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define ADC_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define ADC_REG_H_SW_PATCH_VERSION                        0x00U
  
/**@} end of group ADC_Macros */
/***********************************************************************************************************
                                      VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Adc_Reg.h and Reg_eSys.h */
    #if (ADC_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Adc_Reg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Adc_Reg.h and Reg_eSys.h */
    #if (ADC_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Adc_Reg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
                                             GLOBAL VARIABLE
************************************************************************************************************/
#define ADC_START_SEC_CONST_32
#include "Adc_MemMap.h"

/** @defgroup ADC_Variable
  @{
*/

/** The declaration of the ADC base address array  */
extern CONST(uint32, ADC_CONST) ADC_BASEADDR_ARR[1];

/**@} end of group ADC_Variable */

#define ADC_STOP_SEC_CONST_32
#include "Adc_MemMap.h"
/***********************************************************************************************************
                                            MACRO DEFINITION
************************************************************************************************************/

/** @defgroup ADC_Macros
  @{
*/
/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_STS (Base + 0x00)
************************************************************************************************************/
/** ADC_STS register address */
#define ADC_STS_REG_ADDR(ModId)             ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0U))

#define ADC_STS_ADCRDYFLG_MASK              ((uint32)0x00000001U)
#define ADC_STS_ADCRDYFLG_SHIFT             ((uint8)0U)

#define ADC_STS_EOSMPFLG_MASK               ((uint32)0x00000002U)
#define ADC_STS_EOSMPFLG_SHIFT              ((uint8)1U)

#define ADC_STS_EOCFLG_MASK                 ((uint32)0x00000004U)
#define ADC_STS_EOCFLG_SHIFT                ((uint8)2U)

#define ADC_STS_EOSEQFLG_MASK               ((uint32)0x00000008U)
#define ADC_STS_EOSEQFLG_SHIFT              ((uint8)3U)

#define ADC_STS_OVREFLG_MASK                ((uint32)0x00000010U)
#define ADC_STS_OVREFLG_SHIFT               ((uint8)4U)

#define ADC_STS_AWDFLG_MASK                 ((uint32)0x00000080U)
#define ADC_STS_AWDFLG_SHIFT                ((uint8)7U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_IEN (Base + 0x04)
************************************************************************************************************/
/** ADC_IEN register address */
#define ADC_IEN_REG_ADDR(ModId)             ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x04U))

#define ADC_IEN_ADCRDYIEN_MASK              ((uint32)0x00000001U)
#define ADC_IEN_ADCRDYIEN_SHIFT             ((uint8)0U)

#define ADC_IEN_EOSMPIEN_MASK               ((uint32)0x00000002U)
#define ADC_IEN_EOSMPIEN_SHIFT              ((uint8)1U)

#define ADC_IEN_EOCIEN_MASK                 ((uint32)0x00000004U)
#define ADC_IEN_EOCIEN_SHIFT                ((uint8)2U)

#define ADC_IEN_EOSEQIEN_MASK               ((uint32)0x00000008U)
#define ADC_IEN_EOSEQIEN_SHIFT              ((uint8)3U)

#define ADC_IEN_OVRIEN_MASK                 ((uint32)0x00000010U)
#define ADC_IEN_OVRIEN_SHIFT                ((uint8)4U)

#define ADC_IEN_AWDIEN_MASK                 ((uint32)0x00000080U)
#define ADC_IEN_AWDIEN_SHIFT                ((uint8)7U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_CTRL (Base + 0x08)
************************************************************************************************************/
/** ADC_CTRL register address */
#define ADC_CTRL_REG_ADDR(ModId)            ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x08U))

#define ADC_CTRL_ADCEN_MASK                 ((uint32)0x00000001U)
#define ADC_CTRL_ADCEN_SHIFT                ((uint8)0U)

#define ADC_CTRL_ADCD_MASK                  ((uint32)0x00000002U)
#define ADC_CTRL_ADCD_SHIFT                 ((uint8)1U)

#define ADC_CTRL_STARTCEN_MASK              ((uint32)0x00000004U)
#define ADC_CTRL_STARTCEN_SHIFT             ((uint8)2U)

#define ADC_CTRL_STOPCEN_MASK               ((uint32)0x00000010U)
#define ADC_CTRL_STOPCEN_SHIFT              ((uint8)4U)

#define ADC_CTRL_CAL_MASK                   ((uint32)0x80000000U)
#define ADC_CTRL_CAL_SHIFT                  ((uint8)31U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_CFG1 (Base + 0x0C)
************************************************************************************************************/
/** ADC_CFG1 register address */
#define ADC_CFG1_REG_ADDR(ModId)            ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x0CU))

#define ADC_CFG1_DMAEN_MASK                 ((uint32)0x00000001U)
#define ADC_CFG1_DMAEN_SHIFT                ((uint8)0U)

#define ADC_CFG1_DMACFG_MASK                ((uint32)0x00000002U)
#define ADC_CFG1_DMACFG_SHIFT               ((uint8)1U)

#define ADC_CFG1_SCANSEQDIR_MASK            ((uint32)0x00000004U)
#define ADC_CFG1_SCANSEQDIR_SHIFT           ((uint8)2U)

#define ADC_CFG1_DATARESCFG_MASK            ((uint32)0x00000018U)
#define ADC_CFG1_DATARESCFG_SHIFT           ((uint8)3U)

#define ADC_CFG1_DALIGCFG_MASK              ((uint32)0x00000020U)
#define ADC_CFG1_DALIGCFG_SHIFT             ((uint8)5U)

#define ADC_CFG1_EXTTRGSEL_MASK             ((uint32)0x000001C0U)
#define ADC_CFG1_EXTTRGSEL_SHIFT            ((uint8)6U)

/** Data Resolution */
#define ADC_CFG1_EXTTRGSEL_EVT0             ((uint8)0U)
#define ADC_CFG1_EXTTRGSEL_EVT1             ((uint8)1U)
#define ADC_CFG1_EXTTRGSEL_EVT2             ((uint8)2U)
#define ADC_CFG1_EXTTRGSEL_EVT3             ((uint8)3U)
#define ADC_CFG1_EXTTRGSEL_EVT4             ((uint8)4U)
#define ADC_CFG1_EXTTRGSEL_EVT5             ((uint8)5U)
#define ADC_CFG1_EXTTRGSEL_EVT6             ((uint8)6U)
#define ADC_CFG1_EXTTRGSEL_EVT7             ((uint8)7U)

#define ADC_CFG1_EXTPOLSEL_MASK             ((uint32)0x00000C00U)
#define ADC_CFG1_EXTPOLSEL_SHIFT            ((uint8)10U)

/** External Trigger Enable and Polarity */
#define ADC_CFG1_EXTPOLSEL_DIS              ((uint8)0U)
#define ADC_CFG1_EXTPOLSEL_RISE             ((uint8)1U)
#define ADC_CFG1_EXTPOLSEL_FALL             ((uint8)2U)
#define ADC_CFG1_EXTPOLSEL_RISE_FALL        ((uint8)3U)

#define ADC_CFG1_OVRMAG_MASK                ((uint32)0x00001000U)
#define ADC_CFG1_OVRMAG_SHIFT               ((uint8)12U)

#define ADC_CFG1_CMODESEL_MASK              ((uint32)0x00002000U)
#define ADC_CFG1_CMODESEL_SHIFT             ((uint8)13U)

#define ADC_CFG1_WAITCEN_MASK               ((uint32)0x00004000U)
#define ADC_CFG1_WAITCEN_SHIFT              ((uint8)14U)

#define ADC_CFG1_AOEN_MASK                  ((uint32)0x00008000U)
#define ADC_CFG1_AOEN_SHIFT                 ((uint8)15U)

#define ADC_CFG1_DISCEN_MASK                ((uint32)0x00010000U)
#define ADC_CFG1_DISCEN_SHIFT               ((uint8)16U)

#define ADC_CFG1_AWDCHEN_MASK               ((uint32)0x00400000U)
#define ADC_CFG1_AWDCHEN_SHIFT              ((uint8)22U)

#define ADC_CFG1_AWDEN_MASK                 ((uint32)0x00800000U)
#define ADC_CFG1_AWDEN_SHIFT                ((uint8)23U)

#define ADC_CFG1_AWDCHSEL_MASK              ((uint32)0x7C000000U)
#define ADC_CFG1_AWDCHSEL_SHIFT             ((uint8)26U)

/** Analog Watchdog Channel */
#define ADC_CFG1_AWDCHSEL_CH(ChId)          ((uint8)ChId)
/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_CFG2 (Base + 0x10)
************************************************************************************************************/
/** ADC_CFG2 register address */
#define ADC_CFG2_REG_ADDR(ModId)            ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x10U))

#define ADC_CFG2_CLKCFG_MASK                ((uint32)0xC0000000U)
#define ADC_CFG2_CLKCFG_SHIFT               ((uint8)30U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_SMPTIM (Base + 0x14)
************************************************************************************************************/
/** ADC_SMPTIM register address */
#define ADC_SMPTIM_REG_ADDR(ModId)          ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x14U))

#define ADC_SMPTIM_SMPCYCSEL_MASK           ((uint32)0x00000007U)
#define ADC_SMPTIM_SMPCYCSEL_SHIFT          ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_AWDT (Base + 0x20)
************************************************************************************************************/
/** ADC_AWDT register address */
#define ADC_AWDT_REG_ADDR(ModId)            ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x20U))

#define ADC_AWDT_AWDLT_MASK                 ((uint32)0x00000FFFU)
#define ADC_AWDT_AWDLT_SHIFT                ((uint8)0U)

#define ADC_AWDT_AWDHT_MASK                 ((uint32)0x0FFF0000U)
#define ADC_AWDT_AWDHT_SHIFT                ((uint8)16U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_CHSEL (Base + 0x28)
************************************************************************************************************/
/** ADC_CHSEL register address */
#define ADC_CHSEL_REG_ADDR(ModId)           ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x28U))

#define ADC_CHSEL_CHxSEL_MASK(ChId)         ((uint32)(1U << ChId))
#define ADC_CHSEL_CHxSEL_SHIFT(ChId)        ((uint8)ChId)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_DATA (Base + 0x40)
************************************************************************************************************/
/** ADC_DATA register address */
#define ADC_DATA_REG_ADDR(ModId)            ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x40U))

#define ADC_DATA_CDATA_MASK                 ((uint32)0x0000FFFFU)
#define ADC_DATA_CDATA_SHIFT                ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_ANA_SWITCH (Base + 0x300)
************************************************************************************************************/
/** ADC_ANA_SWITCH register address */
#define ADC_ANA_SWITCH_REG_ADDR(ModId)      ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x300U))

#define ADC_ANA_SWITCH_MASK                 ((uint32)0x00000003U)
#define ADC_ANA_SWITCH_SHIFT                ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: ADC_CCFG (Base + 0x308)
************************************************************************************************************/
/** ADC_CCFG register address */
#define ADC_CCFG_REG_ADDR(ModId)            ((uint32)(ADC_BASEADDR_ARR[ModId] + (uint32)0x308U))

#define ADC_CCFG_VREFEN_MASK                ((uint32)0x00400000U)
#define ADC_CCFG_VREFEN_SHIFT               ((uint8)22U)

#define ADC_CCFG_TSEN_MASK                  ((uint32)0x00800000U)
#define ADC_CCFG_TSEN_SHIFT                 ((uint8)23U)

/**@} end of group ADC_Macros */

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* ADC_REG_H */

/**@} end of group ADC_Driver */
/**@} end of group APM32F4xx_StdPeriphDriver */
