/*!
* @file     Mcu_RcmTypes.h
*
* @version  1.0.0
*
* @brief    Data Type Definition File for the MCU Module Based on RCM IP.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef MCU_RCMTYPES_H
#define MCU_RCMTYPES_H

#ifdef __cplusplus
extern "C" {
#endif

#include "g32a1085.h"
#include "StdRegMacros.h"
#include "Compiler_Cfg.h"
#include "Compiler.h"
#include "Mcu_Cfg.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @addtogroup MCU_Driver
  @{
*/

/** @defgroup MCU_Macros
  @{
*/
/*******************************************************************************
                        VENDOR ID & AUTOSAR VERSION INFO
*******************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define MCU_RCM_TYPES_H_VENDOR_ID                       0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_RCM_TYPES_H_AR_RELEASE_MAJOR_VERSION        0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_RCM_TYPES_H_AR_RELEASE_MINOR_VERSION        0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define MCU_RCM_TYPES_H_AR_RELEASE_REVISION_VERSION     0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_RCM_TYPES_H_SW_MAJOR_VERSION                0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_RCM_TYPES_H_SW_MINOR_VERSION                0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define MCU_RCM_TYPES_H_SW_PATCH_VERSION                0x00U

/**@} end of group MCU_Macros */
/*******************************************************************************
                             VERSION CHECK
*******************************************************************************/


/*******************************************************************************
                            ENUMERATION DEFINITION
*******************************************************************************/
/** @defgroup MCU_Enumerations
  @{
*/

/**
* @brief   HSE enum
*/
typedef enum
{
    RCM_HSE_CLOSE  = 0x00, //!< turn OFF the HSE oscillator
    RCM_HSE_OPEN   = 0x01, //!< turn ON the HSE oscillator
    RCM_HSE_BYPASS = 0x05  //!< HSE oscillator bypassed with external clock
} Mcu_Rcm_HseSelType;

/**
* @brief   System clock select
*/
typedef enum
{
    RCM_PLL_SEL_HSI_DIV2 = 0, //!< HSI clock divided by 2 selected as PLL clock source
    RCM_PLL_SEL_HSE = 1       //!< HSE/CLKDIV1 selected as PLL clock entry
} Mcu_Rcm_PllSelType;

/**
* @brief   PLL multiplication factor
*/
typedef enum
{
    RCM_PLLMF_2,  //!< specifies the PLLMULCFG clock multiple factor as 2
    RCM_PLLMF_3,  //!< specifies the PLLMULCFG clock multiple factor as 3
    RCM_PLLMF_4,  //!< specifies the PLLMULCFG clock multiple factor as 4
    RCM_PLLMF_5,  //!< specifies the PLLMULCFG clock multiple factor as 5
    RCM_PLLMF_6,  //!< specifies the PLLMULCFG clock multiple factor as 6
    RCM_PLLMF_7,  //!< specifies the PLLMULCFG clock multiple factor as 7
    RCM_PLLMF_8,  //!< specifies the PLLMULCFG clock multiple factor as 8
    RCM_PLLMF_9,  //!< specifies the PLLMULCFG clock multiple factor as 9
    RCM_PLLMF_10, //!< specifies the PLLMULCFG clock multiple factor as 10
    RCM_PLLMF_11, //!< specifies the PLLMULCFG clock multiple factor as 11
    RCM_PLLMF_12, //!< specifies the PLLMULCFG clock multiple factor as 12
    RCM_PLLMF_13, //!< specifies the PLLMULCFG clock multiple factor as 13
    RCM_PLLMF_14, //!< specifies the PLLMULCFG clock multiple factor as 14
    RCM_PLLMF_15, //!< specifies the PLLMULCFG clock multiple factor as 15
    RCM_PLLMF_16  //!< specifies the PLLMULCFG clock multiple factor as 16
} Mcu_Rcm_PllmfType;

/**
* @brief   RCM clock division
*/
typedef enum
{
    RCM_CLK_DIV_1,  //!< specifies the PLLDIVCFG clock division factor as 1
    RCM_CLK_DIV_2,  //!< specifies the PLLDIVCFG clock division factor as 2
    RCM_CLK_DIV_3,  //!< specifies the PLLDIVCFG clock division factor as 3
    RCM_CLK_DIV_4,  //!< specifies the PLLDIVCFG clock division factor as 4
    RCM_CLK_DIV_5,  //!< specifies the PLLDIVCFG clock division factor as 5
    RCM_CLK_DIV_6,  //!< specifies the PLLDIVCFG clock division factor as 6
    RCM_CLK_DIV_7,  //!< specifies the PLLDIVCFG clock division factor as 7
    RCM_CLK_DIV_8,  //!< specifies the PLLDIVCFG clock division factor as 8
    RCM_CLK_DIV_9,  //!< specifies the PLLDIVCFG clock division factor as 9
    RCM_CLK_DIV_10, //!< specifies the PLLDIVCFG clock division factor as 10
    RCM_CLK_DIV_11, //!< specifies the PLLDIVCFG clock division factor as 11
    RCM_CLK_DIV_12, //!< specifies the PLLDIVCFG clock division factor as 12
    RCM_CLK_DIV_13, //!< specifies the PLLDIVCFG clock division factor as 13
    RCM_CLK_DIV_14, //!< specifies the PLLDIVCFG clock division factor as 14
    RCM_CLK_DIV_15, //!< specifies the PLLDIVCFG clock division factor as 15
    RCM_CLK_DIV_16  //!< specifies the PLLDIVCFG clock division factor as 16
} Mcu_Rcm_ClkDivType;


/**
* @brief   CMU clock division
*/
typedef enum
{
    CMU_CLK_DIV_1,   //!< specifies the cmu clock division factor as 1
    CMU_CLK_DIV_2,   //!< specifies the cmu clock division factor as 2
    CMU_CLK_DIV_3,   //!< specifies the cmu clock division factor as 3
    CMU_CLK_DIV_4,   //!< specifies the cmu clock division factor as 4
    CMU_CLK_DIV_5,   //!< specifies the cmu clock division factor as 5
    CMU_CLK_DIV_6,   //!< specifies the cmu clock division factor as 6
    CMU_CLK_DIV_7,   //!< specifies the cmu clock division factor as 7
    CMU_CLK_DIV_8,   //!< specifies the cmu clock division factor as 8
    CMU_CLK_DIV_9,   //!< specifies the cmu clock division factor as 9
    CMU_CLK_DIV_10,  //!< specifies the cmu clock division factor as 10
    CMU_CLK_DIV_11,  //!< specifies the cmu clock division factor as 11
    CMU_CLK_DIV_12,  //!< specifies the cmu clock division factor as 12
    CMU_CLK_DIV_13,  //!< specifies the cmu clock division factor as 13
    CMU_CLK_DIV_14,  //!< specifies the cmu clock division factor as 14
    CMU_CLK_DIV_15,  //!< specifies the cmu clock division factor as 15
    CMU_CLK_DIV_16,  //!< specifies the cmu clock division factor as 16
    CMU_CLK_DIV_17,  //!< specifies the cmu clock division factor as 17
    CMU_CLK_DIV_18,  //!< specifies the cmu clock division factor as 18
    CMU_CLK_DIV_19,  //!< specifies the cmu clock division factor as 19
    CMU_CLK_DIV_20,  //!< specifies the cmu clock division factor as 20
    CMU_CLK_DIV_21,  //!< specifies the cmu clock division factor as 21
    CMU_CLK_DIV_22,  //!< specifies the cmu clock division factor as 22
    CMU_CLK_DIV_23,  //!< specifies the cmu clock division factor as 23
    CMU_CLK_DIV_24,  //!< specifies the cmu clock division factor as 24
    CMU_CLK_DIV_25,  //!< specifies the cmu clock division factor as 25
    CMU_CLK_DIV_26,  //!< specifies the cmu clock division factor as 26
    CMU_CLK_DIV_27,  //!< specifies the cmu clock division factor as 27
    CMU_CLK_DIV_28,  //!< specifies the cmu clock division factor as 28
    CMU_CLK_DIV_29,  //!< specifies the cmu clock division factor as 29
    CMU_CLK_DIV_30,  //!< specifies the cmu clock division factor as 30
    CMU_CLK_DIV_31,  //!< specifies the cmu clock division factor as 31
    CMU_CLK_DIV_32,  //!< specifies the cmu clock division factor as 32
    CMU_CLK_DIV_33,  //!< specifies the cmu clock division factor as 33
    CMU_CLK_DIV_34,  //!< specifies the cmu clock division factor as 34
    CMU_CLK_DIV_35,  //!< specifies the cmu clock division factor as 35
    CMU_CLK_DIV_36,  //!< specifies the cmu clock division factor as 36
    CMU_CLK_DIV_37,  //!< specifies the cmu clock division factor as 37
    CMU_CLK_DIV_38,  //!< specifies the cmu clock division factor as 38
    CMU_CLK_DIV_39,  //!< specifies the cmu clock division factor as 39
    CMU_CLK_DIV_40,  //!< specifies the cmu clock division factor as 40
    CMU_CLK_DIV_41,  //!< specifies the cmu clock division factor as 41
    CMU_CLK_DIV_42,  //!< specifies the cmu clock division factor as 42
    CMU_CLK_DIV_43,  //!< specifies the cmu clock division factor as 43
    CMU_CLK_DIV_44,  //!< specifies the cmu clock division factor as 44
    CMU_CLK_DIV_45,  //!< specifies the cmu clock division factor as 45
    CMU_CLK_DIV_46,  //!< specifies the cmu clock division factor as 46
    CMU_CLK_DIV_47,  //!< specifies the cmu clock division factor as 47
    CMU_CLK_DIV_48,  //!< specifies the cmu clock division factor as 48
    CMU_CLK_DIV_49,  //!< specifies the cmu clock division factor as 49
    CMU_CLK_DIV_50   //!< specifies the cmu clock division factor as 50
} Mcu_Cmu_ClkDivType;


/**
* @brief   Clock output control
*/
typedef enum
{
    RCM_COC_NO_CLOCK,     //!< No clock selected
    RCM_COC_HSI14,        //!< HSI14 oscillator clock selected
    RCM_COC_LSI,          //!< LSI oscillator clock selected
    RCM_COC_LSE,          //!< LSE oscillator clock selected
    RCM_COC_SYSCLK,       //!< System clock selected
    RCM_COC_HSI,          //!< HSI oscillator clock selected
    RCM_COC_HSE,          //!< HSE oscillator clock selected
    RCM_COC_PLLCLK_DIV_2  //!< PLL clock divided by 2 selected
} Mcu_Rcm_CocClkType;

/**
* @brief   System clock select
*/
typedef enum
{
    RCM_SYSCLK_SEL_HSI,     //!< HSI selected as system clock source
    RCM_SYSCLK_SEL_HSE,     //!< HSE selected as system clock source
    RCM_SYSCLK_SEL_PLL      //!< PLL selected as system clock source
} Mcu_Rcm_SyscSelType;


#if (MCU_INITCLK_ENABLED == STD_ON)
/**
* @brief   AHB divider Number
*/
typedef enum
{
    RCM_SYSCLK_DIV_1 = 7, //!< AHB clock = SYSCLK
    RCM_SYSCLK_DIV_2,     //!< AHB clock = SYSCLK/2
    RCM_SYSCLK_DIV_4,     //!< AHB clock = SYSCLK/4
    RCM_SYSCLK_DIV_8,     //!< AHB clock = SYSCLK/8
    RCM_SYSCLK_DIV_16,    //!< AHB clock = SYSCLK/16
    RCM_SYSCLK_DIV_64,    //!< AHB clock = SYSCLK/64
    RCM_SYSCLK_DIV_128,   //!< AHB clock = SYSCLK/128
    RCM_SYSCLK_DIV_256,   //!< AHB clock = SYSCLK/256
    RCM_SYSCLK_DIV_512    //!< AHB clock = SYSCLK/512
} Mcu_Rcm_AHBDivType;


/**
* @brief   APB divider Number
*/
typedef enum
{
    RCM_HCLK_DIV_1 = 3,  //!< APB clock = HCLK
    RCM_HCLK_DIV_2,      //!< APB clock = HCLK/2
    RCM_HCLK_DIV_4,      //!< APB clock = HCLK/4
    RCM_HCLK_DIV_8,      //!< APB clock = HCLK/8
    RCM_HCLK_DIV_16      //!< APB clock = HCLK/16
} Mcu_Rcm_APBDivType;


/**
* @brief   USART clock source select
*/
typedef enum
{
    RCM_USARTCLK_PCLK    = ((uint32)0x00000000),  //!< USART clock = APB Clock (PCLK)
    RCM_USARTCLK_SYSCLK  = ((uint32)0x00000005),  //!< USART clock = System Clock
    RCM_USARTCLK_HSI     = ((uint32)0x0000000F),  //!< USART clock = HSI Clock
    RCM_CANCLK_HSE       = ((uint32)0x10000000),  //!< CAN clock = APB Clock (PCLK)
    RCM_CANCLK_PLL       = ((uint32)0x00001000)   //!< CAN clock = System Clock
} Mcu_Rcm_Cfg3ClkType;


typedef enum
{
    DMA1_MODULE   = 0x00,
    SRAM_MODULE   = 0x01,
    FMC_MODULE    = 0x02,
    CRC_MODULE    = 0x03,
    RNG_MODULE    = 0x04,
    SHA_MODULE    = 0x05,
    AES_MODULE    = 0x06,
    GPIOA_MODULE  = 0x07,
    GPIOB_MODULE  = 0x08,
    GPIOC_MODULE  = 0x09,
    GPIOD_MODULE  = 0x0A,
    GPIOF_MODULE  = 0x0B,
    SYSCFG_MODULE = 0x0C,
    ADC_MODULE    = 0x0D,
    TMR1_MODULE   = 0x0E,
    SPI_MODULE    = 0x0F,
    USART1_MODULE = 0x10,
    TMR8_MODULE   = 0x11,
    DBGMCU_MODULE = 0x12,
    SERM_MODULE   = 0x13,
    TMR2_MODULE   = 0x14,
    TMR3_MODULE   = 0x15,
    TMR4_MODULE   = 0x16,
    TMR6_MODULE   = 0x17,
    TMR7_MODULE   = 0x18,
    USART2_MODULE = 0x19,
    FDCAN_MODULE  = 0x1A,
    PMU_MODULE    = 0x1B
} Mcu_Rcm_ModuleNumType;
#endif

/**
* @brief   CEC divider Number
*/
typedef enum
{
    RCM_CECCLK_HSI_DIV_224, //!< CEC clock = HSI/244 (32768Hz)
    RCM_CECCLK_LSI_DIV      //!< CEC clock = LSI
} Mcu_Rcm_CecClkType;


/**
* @brief   USART clock source selectio
*/
typedef enum
{
    RCM_USART1_SEL  = 0x00, //!< USART1
    RCM_USART2_SEL  = 0x01, //!< USART2
    RCM_CANFD_SEL   = 0x02  //!< CANFD
} Mcu_Rcm_Cfg3SelType;


/**
* @brief   RTC clock select
*/
typedef enum
{
    RCM_RTCCLK_NONE = 0x00,
    RCM_RTCCLK_LSI = 0x02,        //!< LSI selected as RTC clock
    RCM_RTCCLK_HSE_DIV_32 = 0x03  //!< HSE divided by 32 selected as RTC clock
} Mcu_Rcm_RtcClkType;


typedef enum
{
    RCM_AHB_PERIPH,
    RCM_APB1_PERIPH,
    RCM_APB2_PERIPH,
    RCM_RTC_PERIPH
} Mcu_Rcm_PeriphSelType;

/**
* @brief   AHB peripheral
*/
typedef enum
{
    RCM_AHBRST_TRNG     = BIT7,   //!< TRNG
    RCM_AHBRST_SHAEN    = BIT8,   //!< SHAEN
    RCM_AHBRST_AES256EN = BIT9,   //!< AES256EN
    RCM_AHBRST_PARST    = BIT17,  //!< PARST
    RCM_AHBRST_PBRST    = BIT18,  //!< PBRST
    RCM_AHBRST_PCRST    = BIT19,  //!< PCRST
    RCM_AHBRST_PDRST    = BIT20,  //!< PDRST
    RCM_AHBRST_PERST    = BIT22,  //!< PERST

    RCM_AHBRST1_TMR2    = BIT0,   //!< TMR2
    RCM_AHBRST1_TMR3    = BIT1,   //!< TMR3
    RCM_AHBRST1_TMR4    = BIT2,   //!< TMR4
    RCM_AHBRST1_TMR6    = BIT4,   //!< TMR6
    RCM_AHBRST1_TMR7    = BIT5,   //!< TMR7
    RCM_AHBRST1_WWDT    = BIT11,  //!< WWDT
    RCM_AHBRST1_USART2  = BIT17,  //!< USART2
    RCM_AHBRST1_CAN     = BIT25,  //!< CAN
    RCM_AHBRST1_PMU     = BIT28,  //!< PMU
    
    RCM_AHBRST2_SYSCFG  = BIT0,   //!< SYSCFG
    RCM_AHBRST2_ADC     = BIT9,   //!< ADC
    RCM_AHBRST2_TMR1    = BIT11,  //!< TMR1
    RCM_AHBRST2_SPI1    = BIT12,  //!< SPI1
    RCM_AHBRST2_USART1  = BIT14,  //!< USART1
    RCM_AHBRST2_TIM8    = BIT15,  //!< TIM8
    RCM_AHBRST2_DBG     = BIT22,  //!< DBG
    RCM_AHBRST2_SMS     = BIT23,  //!< SMS
    
    RCM_RTCCTRL_RTC     = BIT16   //!< RTC
} Mcu_Rcm_ModeResetType;


/**
* @brief   AHB peripheral
*/
typedef enum
{
    RCM_AHB_PERIPH_DMA1     = BIT0,  //!< DMA1 peripheral clock
    RCM_AHB_PERIPH_SRAM     = BIT2,  //!< SRAM peripheral clock
    RCM_AHB_PERIPH_FMC      = BIT4,  //!< SRAM peripheral clock
    RCM_AHB_PERIPH_CRC      = BIT6,  //!< CRC peripheral clock
    RCM_AHB_PERIPH_RNG      = BIT7,  //!< RNG peripheral clock
    RCM_AHB_PERIPH_SHA      = BIT8,  //!< SHA peripheral clock
    RCM_AHB_PERIPH_AES      = BIT9,  //!< AES peripheral clock
    RCM_AHB_PERIPH_GPIOA    = BIT17, //!< GPIOA peripheral clock
    RCM_AHB_PERIPH_GPIOB    = BIT18, //!< GPIOB peripheral clock
    RCM_AHB_PERIPH_GPIOC    = BIT19, //!< GPIOC peripheral clock
    RCM_AHB_PERIPH_GPIOD    = BIT20, //!< GPIOD peripheral clock
    RCM_AHB_PERIPH_GPIOF    = BIT22  //!< GPIOF peripheral clock
} Mcu_Rcm_AHBPeriphType;


/**
* @brief   AHB2 peripheral
*/
typedef enum
{
    RCM_APB2_PERIPH_SYSCFG  = BIT0,  //!< SYSCFG peripheral clock
    RCM_APB2_PERIPH_ADC1    = BIT9,  //!< ADC1 peripheral clock
    RCM_APB2_PERIPH_TMR1    = BIT11, //!< TMR1 peripheral clock
    RCM_APB2_PERIPH_SPI1    = BIT12, //!< SPI1 peripheral clock
    RCM_APB2_PERIPH_USART1  = BIT14, //!< USART1 peripheral clock
    RCM_APB2_PERIPH_TMR8    = BIT15, //!< TMR8 peripheral clock
    RCM_APB2_PERIPH_DBGMCU  = BIT22, //!< DBGMCU peripheral clock
    RCM_APB2_PERIPH_SERM    = BIT23  //!< SERM peripheral clock
} Mcu_Rcm_APB2PeriphType;


/**
* @brief   AHB1 peripheral
*/
typedef enum
{
    RCM_APB1_PERIPH_TMR2    = BIT0,  //!< TMR2 peripheral clock
    RCM_APB1_PERIPH_TMR3    = BIT1,  //!< TMR3 peripheral clock
    RCM_APB1_PERIPH_TMR4    = BIT2,  //!< TMR4 peripheral clock
    RCM_APB1_PERIPH_TMR6    = BIT4,  //!< TMR6 peripheral clock
    RCM_APB1_PERIPH_TMR7    = BIT5,  //!< TMR7 peripheral clock
    RCM_APB1_PERIPH_USART2  = BIT17, //!< USART2 peripheral clock
    RCM_APB1_PERIPH_FDCAN   = BIT25, //!< FDCAN peripheral clock
    RCM_APB1_PERIPH_PMU     = BIT28  //!< PMU peripheral clock
} Mcu_Rcm_APB1PeriphType;


typedef enum
{
    /* Generic error codes */
    STATUS_SUCCESS      = 0x0000U,  //!< Generic success status
    STATUS_ERROR        = 0x0001U,  //!< Generic failure status
    STATUS_BUSY         = 0x0002U,  //!< Generic busy status
    STATUS_TIMEOUT      = 0x0003U,  //!< Generic timeout status
    STATUS_UNSUPPORTED  = 0x0004U   //!< Generic unsupported status
} Mcu_Rcm_StatusType;


/*!
* @brief SCG system OSC monitor mode.
*/
typedef enum
{
    SCG_SOSC_MONITOR_DISABLE = 0U,  //!< Monitor disable.
    SCG_SOSC_MONITOR_INT     = 1U,  //!< Interrupt when system OSC error detected.
    SCG_SOSC_MONITOR_RESET   = 2U   //!< Reset when system OSC error detected.
} Mcu_Rcm_SoscMonitorModeType;


/*!
* @brief SCG OSC external reference clock select.
*/
typedef enum
{
    SCG_SOSC_REF_EXT   = 0x0,   //!< External reference clock requested
    SCG_SOSC_REF_OSC   = 0x1    //!< Internal oscillator of OSC requested.
} Mcu_Rcm_SoscExtRefType;


/*!
* @brief SCG OSC high gain oscillator select.
*/
typedef enum
{
    SCG_SOSC_GAIN_LOW    = 0x0,  //!< Configure crystal oscillator for low-power operation
    SCG_SOSC_GAIN_HIGH   = 0x1   //!< Configure crystal oscillator for high-gain operation
} Mcu_Rcm_SoscGainType;


/*!
* @brief SCG OSC frequency range select
*/
typedef enum
{
    SCG_SOSC_RANGE_MID    = 2U,  //!< Medium frequency range selected for the crystal OSC (4 Mhz to 8 Mhz).
    SCG_SOSC_RANGE_HIGH   = 3U   //!< High frequency range selected for the crystal OSC (8 Mhz to 40 Mhz).
} Mcu_Rcm_SoscRangeType;


/*!
* @brief clk select
*/
typedef enum
{
    HSICLK_CLK,  //!< hsi clock select
    HSECLK_CLK,  //!< hse clock select
    PLLCLK_CLK   //!< pll clock select
} Mcu_Rcm_SysClkSelType;


typedef enum
{
    CLK_ENABLE  = 0x0,
    CLK_DISABLE = 0x1
} Mcu_Rcm_ClockEnType;


/*!
* @brief run mode config
*/
typedef enum
{
    MCU_SLEEP_MODE = 0x00,  //!< sleep mode
    MCU_STOP_MODE = 0x01,  //!< stop mode
    MCU_STABDBY_MODE = 0x02  //!< stabdby mode
} Mcu_Pmu_ModeCfgType;


typedef enum
{
    RCM_FREQ_UNDER_ERR_IRQ = 0U,
    RCM_FREQ_OVER_ERR_IRQ = 1U,
    RCM_CLOCK_LOST_ERR_IRQ = 2U,
    RCM_CLOCK_SYS_ERR_IRQ = 3U,
    
    RCM_LSI_READY_INT_IRQ = 4U,
    RCM_HSI_READY_INT_IRQ = 5U,
    RCM_HSE_READY_INT_IRQ = 6U,
    RCM_PLL_READY_INT_IRQ = 7U,
    RCM_HSI14_READY_INT_IRQ = 8U,
    
    RCM_CMU_LOC_INT_IRQ = 9U
} Mcu_Rcm_IrqType;

typedef enum
{
    MCU_PLL_UNLOCKED = 0U,    /* SYSPLL locked status */
    MCU_PLL_LOCKED = 1U,      /* SYSPLL unlocked status */
    MCU_PLL_STATUS_UNDEFINED = 2U 
} Mcu_PllStatusType;


typedef enum
{
    CMU_MEASURE_HSI = 0U,    /* Measure HSI Clock */
    CMU_MEASURE_PLL = 1U     /* Measure PLL Clock */
} Mcu_Cmu_ClockSelectType;

typedef enum
{
    CMU_FLLIE_INTER = 0x00000100U,  /* Measure HSI Clock */
    CMU_FHHIE_INTER = 0x00000200U,  /* Measure PLL Clock */
    CMU_LOCIE_INTER = 0x00000400U   /* Measure PLL Clock */
} Mcu_Cmu_InterrputType;


/**@} end of group MCU_Enumerations */
/*******************************************************************************
                            STRUCT DEFINITION
*******************************************************************************/
/** @defgroup MCU_Typedef
  @{
*/

/**
 * @brief   This type specifies the reset reason in raw register format read from a reset status register.
 */
typedef uint32  Mcu_RawResetType;

/**@} end of group MCU_Typedef */

/** @defgroup MCU_Structure
  @{
*/

/*!
* @brief hsi clock config
*/
typedef struct
{
    Mcu_Rcm_ClockEnType enableHsiClock; //!< hsi clock enable
    uint8 hsiTrim;
} Mcu_Rcm_HsiClockCfgType;

/*!
* @brief hse clock config
*/
typedef struct
{
    Mcu_Rcm_ClockEnType enableHseClock; //!< hse clock enable
} Mcu_Rcm_HseClockCfgType;

/*!
* @brief pll clock config
*/
typedef struct
{
    Mcu_Rcm_ClockEnType enablePllClock;  //!< pll clock enable
    Mcu_Rcm_PllSelType  pllSelect;  //!< PLL clock source selection
    Mcu_Rcm_PllmfType   pllMf;  //!< PLL frequency multiplication
    Mcu_Rcm_ClkDivType  pllDiv; //!< If the clock source is set to HSE, select its divider
} Mcu_Rcm_PllClockCfgType;


#if (MCU_INITCLK_ENABLED == STD_ON)
/*!
* @brief All Module Clock Enable Switches
*/
typedef struct
{
    Mcu_Rcm_ModuleNumType module;
    Mcu_Rcm_ClockEnType   enable;
} Mcu_Rcm_ModuleClkCfgType;


/*!
* @brief HSI14 Clock Enable and Configuration
*/
typedef struct
{
    Mcu_Rcm_ClockEnType enableHsi14Clock;   //!< enable hsi14
    uint8             hsi14Trim;
} Mcu_Rcm_Hsi14ClockCfgType;


/*!
* @brief rtc Enable and Configuration
*/
typedef struct
{
    Mcu_Rcm_ClockEnType  enable;    //!< enable rtc clock
    Mcu_Rcm_RtcClkType   rtcClk;
} Mcu_Rcm_RtcClockCfgType;

#endif


#if (MCU_INITCLK_ENABLED == STD_ON)
/*!
* @brief mcu clock config
*/
typedef struct
{
    uint32  clockNum;     //!< clock num
    
    Mcu_Rcm_AHBDivType    AHBDiv;   //!< Frequency Division of the AHB Clock Bus
    Mcu_Rcm_APBDivType    APBDiv;   //!< Frequency Division of the APB Clock Bus
    
    const Mcu_Rcm_ModuleClkCfgType * moduleConfig;   //!< module clock conifg ptr
    
    Mcu_Rcm_Hsi14ClockCfgType hsi14ClkCfg;   //!< HSI14 Clock Enable and Configuration
    
    Mcu_Rcm_ClockEnType enableHsi14ADC;   //!< Can the ADC start HSI14
    
    Mcu_Rcm_ClockEnType lsiEnable;   //!< LSI Clock enable or disable
    
    Mcu_Rcm_Cfg3ClkType usart1ClkSele;   //!< Clock source selection for USART1
    Mcu_Rcm_Cfg3ClkType usart2ClkSele;   //!< Clock source selection for USART2
    Mcu_Rcm_Cfg3ClkType canFdClkSele;   //!< Clock source selection for CAN
    
    Mcu_Rcm_ClockEnType CCSEnable;   //!< CCS enable or disable
    
    Mcu_Rcm_RtcClockCfgType rtcCfg;   //!< rtc Enable and Configuration
} Mcu_Rcm_SysClockCfgType;
#endif


/*!
* @brief mcu rcm config
*/
typedef struct
{
    Mcu_Rcm_SysClkSelType    clockSource;   //!< System Clock Selection
    Mcu_Rcm_HsiClockCfgType  hsiClockCfg;   //!< hsi clock config
    Mcu_Rcm_HseClockCfgType  hseClockCfg;   //!< hse clock config
    Mcu_Rcm_PllClockCfgType  pllClockCfg;   //!< pll clock config
} Mcu_Rcm_ConfigType;

/*!
* @brief mcu cmu config
*/
typedef struct
{
    Mcu_Cmu_ClkDivType  cmuRefPre;          //!< System Clock Selection
    Mcu_Cmu_ClockSelectType selectClock;    //!< hsi clock config
    uint8 LOCResetEnable;                   //!< hse clock config
    uint8 clockCount;                       //!< pll clock config
    uint32 fhVal;
    uint32 flVal;
    uint8 locieEna;
} Mcu_Cmu_ConfigType;

/**@} end of group MCU_Structure */
/*******************************************************************************
                            FUNCTION DECLARATION
*******************************************************************************/
#define MCU_START_SEC_CODE
#include "Mcu_MemMap.h"

/** @defgroup MCU_Fuctions
  @{
*/

FUNC(Mcu_Rcm_StatusType, MCU_CODE) Mcu_Rcm_Init(const Mcu_Rcm_ConfigType * clockSourceConfig);

FUNC(Mcu_RawResetType, MCU_CODE) Mcu_Rcm_ReadResetFlag(void);
FUNC(void, MCU_CODE) Mcu_Rcm_ClearResetFlag(void);
FUNC(Mcu_PllStatusType, MCU_CODE) Mcu_Rcm_GetPllState(void);
FUNC(void, MCU_CODE) Mcu_Rcm_CM4SysReset(void);

FUNC(void, MCU_CODE) Mcu_Rcm_ConfigHSE(Mcu_Rcm_HseSelType state);
FUNC(uint8, MCU_CODE) Mcu_Rcm_WaitHSEReady(void);
FUNC(uint8, MCU_CODE) Mcu_Rcm_WaitHSIReady(void);
FUNC(void, MCU_CODE) Mcu_Rcm_SetHSITrim(uint8 hsiTrim);
FUNC(void, MCU_CODE) Mcu_Rcm_EnableHSI(void);
FUNC(void, MCU_CODE) Mcu_Rcm_DisableHSI(void);

FUNC(void, MCU_CODE) Mcu_Rcm_OperationHSI14ADC(Mcu_Rcm_ClockEnType hsi14ADC);
FUNC(uint8, MCU_CODE) Mcu_Rcm_OperationLSI(Mcu_Rcm_ClockEnType lsiEna);

FUNC(void, MCU_CODE) Mcu_Rcm_ConfigPLL(Mcu_Rcm_PllSelType pllSelect, Mcu_Rcm_PllmfType pllMf);
FUNC(void, MCU_CODE) Mcu_Rcm_EnablePLL(void);
FUNC(void, MCU_CODE) Mcu_Rcm_DisablePLL(void);

FUNC(void, MCU_CODE) Mcu_Rcm_ConfigClkDiv(Mcu_Rcm_ClkDivType state);
FUNC(void, MCU_CODE) Mcu_Rcm_OperationCCS(Mcu_Rcm_ClockEnType ccsEna);
void Mcu_Rcm_ConfigCOC(Mcu_Rcm_CocClkType cocClock);

FUNC(void, MCU_CODE) Mcu_Rcm_ConfigSYSCLK(Mcu_Rcm_SyscSelType sysClkSelect);
FUNC(Mcu_Rcm_SyscSelType, MCU_CODE) Mcu_Rcm_ReadSYSCLKSource(void);

#if (MCU_INITCLK_ENABLED == STD_ON)
FUNC(void, MCU_CODE) Mcu_Rcm_ConfigAHB(Mcu_Rcm_AHBDivType AHBDiv);
FUNC(void, MCU_CODE) Mcu_Rcm_ConfigAPB(Mcu_Rcm_APBDivType APBDiv);
FUNC(uint8, MCU_CODE) Mcu_Rcm_OperationHSI14(Mcu_Rcm_Hsi14ClockCfgType hsi14ClkCfg);
FUNC(void, MCU_CODE) Mcu_Rcm_ConfigUsartOrCanClk(Mcu_Rcm_Cfg3SelType cfg3Sel,
                                                 Mcu_Rcm_Cfg3ClkType clk);
FUNC(void, MCU_CODE) Mcu_Rcm_ConfigRTC(Mcu_Rcm_RtcClockCfgType rtcCfg);
#endif

void Mcu_Rcm_ConfigCecClk(Mcu_Rcm_CecClkType CECClk);

FUNC(uint32, MCU_CODE) Mcu_Rcm_ReadSYSCLKFreq(void);
FUNC(uint32, MCU_CODE) Mcu_Rcm_ReadHCLKFreq(void);
FUNC(uint32, MCU_CODE) Mcu_Rcm_ReadPCLKFreq(void);
FUNC(uint32, MCU_CODE) Mcu_Rcm_ReadUSART1CLKFreq(void);

FUNC(void, MCU_CODE) Mcu_Rcm_OperationPeriphClock(uint32 state,
                                                  Mcu_Rcm_PeriphSelType mode,
                                                  uint32 Periph);
FUNC(void, MCU_CODE) Mcu_Rcm_OperationPeriphReset(uint32 state,
                                                  Mcu_Rcm_PeriphSelType mode,
                                                  Mcu_Rcm_ModeResetType Periph);

FUNC(void, MCU_CODE) Mcu_Rcm_EnableInterrupt(Mcu_Rcm_IrqType interrupt);
FUNC(void, MCU_CODE) Mcu_Rcm_DisableInterrupt(Mcu_Rcm_IrqType interrupt);

FUNC(void, USART_CODE) RCM_IRQHandler(void);
FUNC(void, USART_CODE) PVD_IRQHandler(void);

#if (MCU_CMU_MODE_ENABLE == STD_ON)
FUNC(void, MCU_CODE) Mcu_Cmu_ConfigReferenceClock(Mcu_Cmu_ClkDivType cmuRefPre);
FUNC(void, MCU_CODE) Mcu_Cmu_MeasureClockSelect(Mcu_Cmu_ClockSelectType selectClock);
FUNC(void, MCU_CODE) Mcu_Cmu_LOCResetEnable(uint8 status);
FUNC(void, MCU_CODE) Mcu_Cmu_ReferenceClockCounts(uint8 count);
FUNC(void, MCU_CODE) Mcu_Cmu_Enable(uint8 status);
FUNC(void, MCU_CODE) Mcu_Cmu_InterruptEnable(Mcu_Cmu_InterrputType intSelet,uint8 status);
FUNC(uint16, MCU_CODE) Mcu_Cmu_GetMeasValue(void);
#endif

/**@} end of group MCU_Fuctions */

#define MCU_STOP_SEC_CODE
#include "Mcu_MemMap.h"

#ifdef __cplusplus
}
#endif

#endif

/**@} end of group MCU_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
