/*!
* @file     Port_Cfg.h
*
* @version  1.0.0
*
* @brief    This file includes the configuration parameters of the Port module.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef PORT_CFG_H
#define PORT_CFG_H

#ifdef __cplusplus
extern "C" {
#endif  /* ifdef __cplusplus */

#include "Mcal.h"
#include "StdRegMacros.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup PORT_Driver
  @{
*/

/** @defgroup PORT_Macros
  @{
*/
/*******************************************************************************
                        VENDOR ID & AUTOSAR VERSION INFO
*******************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define PORT_CFG_H_VENDOR_ID                        0x00C1U
/** Module ID of this module, as defined in the BSW Module List. */
#define PORT_CFG_H_MODULE_ID                        0x0065U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PORT_CFG_H_AR_RELEASE_MAJOR_VERSION         0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PORT_CFG_H_AR_RELEASE_MINOR_VERSION         0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define PORT_CFG_H_AR_RELEASE_REVISION_VERSION      0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PORT_CFG_H_SW_MAJOR_VERSION                 0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PORT_CFG_H_SW_MINOR_VERSION                 0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define PORT_CFG_H_SW_PATCH_VERSION                 0x00U

/*******************************************************************************
                            MACRO DEFINITION
*******************************************************************************/
/** The max count of the pins supported */
#define PORT_MAX_PIN_COUNT              ((uint16)55)

/** The max count of the configured pins */
#define PORT_MAX_CONFIG_PIN_COUNT       ((uint16)8)

/** The symbolic names of the port pin */
#define PortConfigSet_PortContainer_0_UART1_RX   (0)
#define PortConfigSet_PortContainer_0_UART1_TX   (1)
#define PortConfigSet_PortContainer_0_TMR1_CH1   (2)
#define PortConfigSet_PortContainer_0_TMR1_CH1N  (3)
#define PortConfigSet_PortContainer_0_TMR1_CH2   (4)
#define PortConfigSet_PortContainer_0_TMR1_CH2N  (5)
#define PortConfigSet_PortContainer_0_TMR2_CH1   (6)
#define PortConfigSet_PortContainer_0_TMR3_CH1   (7)

/** Enable or disable the Port_SetPinDirection API */
#define PORT_SET_PINDIRECTION_API       (STD_ON)

/** Enable/disable Port_GetVersionInfo API */
#define PORT_VERINFO_API                (STD_ON)

/** Enable/disable Port_SetPinMode API */
#define PORT_SET_PINMODE_API            (STD_ON)

/** Enable/disable development error detection */
#define PORT_DEV_ERR_DETECT_ENABLE      (STD_ON)

/** Enable/disable debug IO */
#define PORT_DEBUG_IO                   (STD_ON)
#if (STD_OFF == PORT_DEBUG_IO)
    _Pragma("message \"When you configure the functions of the PA13 and PA14 pins for other purposes, it may result in the inability to debug!\"")
#endif

/* PA0 */
#define    PA0_USART2_CTS       (GPIO_MODE_AF1)
#define    PA0_TMR2_CH1         (GPIO_MODE_AF2)
#define    PA0_CANFD_RX         (GPIO_MODE_AF4)
/* PA1 */
#define    PA1_EVENTOUT         (GPIO_MODE_AF0)
#define    PA1_USART2_RTS       (GPIO_MODE_AF1)
#define    PA1_TMR2_CH1         (GPIO_MODE_AF2)
#define    PA1_CANFD_TX         (GPIO_MODE_AF4)
#define    PA1_TMR4_CH2         (GPIO_MODE_AF5)
/* PA2 */
#define    PA2_TMR4_CH1         (GPIO_MODE_AF0)
#define    PA2_USART2_TX        (GPIO_MODE_AF1)
#define    PA2_TMR2_CH3         (GPIO_MODE_AF2)
/* PA3 */
#define    PA3_TMR4_CH2         (GPIO_MODE_AF0)
#define    PA3_USART2_RX        (GPIO_MODE_AF1)
#define    PA3_TMR2_CH4         (GPIO_MODE_AF2)
/* PA4 */
#define    PA4_SPI1_NSS         (GPIO_MODE_AF0)
#define    PA4_USART2_CK        (GPIO_MODE_AF1)
#define    PA4_TMR4_CH1         (GPIO_MODE_AF3)
/* PA5 */
#define    PA5_SPI1_SCK         (GPIO_MODE_AF0)
#define    PA5_TMR2_CH1         (GPIO_MODE_AF2)
/* PA6 */
#define    PA6_SPI1_MISO        (GPIO_MODE_AF0)
#define    PA6_TMR3_CH1         (GPIO_MODE_AF1)
#define    PA6_TMR1_BKIN        (GPIO_MODE_AF2)
#define    PA6_CANFD_RX         (GPIO_MODE_AF4)
#define    PA6_TMR4_CH3         (GPIO_MODE_AF5)
#define    PA6_EVENTOUT         (GPIO_MODE_AF6)
/* PA7 */
#define    PA7_SPI1_MOSI        (GPIO_MODE_AF0)
#define    PA7_TMR3_CH2         (GPIO_MODE_AF1)
#define    PA7_TMR1_CH1N        (GPIO_MODE_AF2)
#define    PA7_CANFD_TX         (GPIO_MODE_AF4)
#define    PA7_TMR4_CH4         (GPIO_MODE_AF5)
#define    PA7_EVENTOUT         (GPIO_MODE_AF6)
/* PA8 */
#define    PA8_MCO              (GPIO_MODE_AF0)
#define    PA8_USART1_CK        (GPIO_MODE_AF1)
#define    PA8_TMR1_CH1         (GPIO_MODE_AF2)
#define    PA8_EVENTOUT         (GPIO_MODE_AF3)
/* PA9 */
#define    PA9_TMR4_CH3         (GPIO_MODE_AF0)
#define    PA9_USART1_TX        (GPIO_MODE_AF1)
#define    PA9_TMR1_CH2         (GPIO_MODE_AF2)
/* PA10 */
#define    PA10_USART1_RX       (GPIO_MODE_AF1)
#define    PA10_TMR1_CH3        (GPIO_MODE_AF2)
/* PA11 */
#define    PA11_EVENTOUT        (GPIO_MODE_AF0)
#define    PA11_USART1_CTS      (GPIO_MODE_AF1)
#define    PA11_TMR1_CH4        (GPIO_MODE_AF2)
#define    PA11_CANFD_RX        (GPIO_MODE_AF4)
/* PA12 */
#define    PA12_EVENTOUT        (GPIO_MODE_AF0)
#define    PA12_USART1_RTS      (GPIO_MODE_AF1)
#define    PA12_TMR1_ETR        (GPIO_MODE_AF2)
#define    PA12_TMR4_CH4        (GPIO_MODE_AF3)
#define    PA12_CANFD_TX        (GPIO_MODE_AF4)
/* PA13 */
#define    PA13_SWDIO           (GPIO_MODE_AF0)
/* PA14 */
#define    PA14_SWCLK           (GPIO_MODE_AF0)
#define    PA14_USART2_TX       (GPIO_MODE_AF1)
/* PA15 */
#define    PA15_SPI1_NSS        (GPIO_MODE_AF0)
#define    PA15_USART2_RX       (GPIO_MODE_AF1)
#define    PA15_TMR2_CH1        (GPIO_MODE_AF2)
#define    PA15_EVENTOUT        (GPIO_MODE_AF3)
/* PB0 */
#define    PB0_USART1_TX        (GPIO_MODE_AF0)
#define    PB0_TMR3_CH3         (GPIO_MODE_AF1)
#define    PB0_TMR1_CH2N        (GPIO_MODE_AF2)
/* PB1 */
#define    PB1_USART1_RX        (GPIO_MODE_AF0)
#define    PB1_TMR3_CH4         (GPIO_MODE_AF1)
#define    PB1_TMR1_CH3N        (GPIO_MODE_AF2)
/* PB2 */
#define    PB2_TMR1_CH1N        (GPIO_MODE_AF2)
/* PB3 */
#define    PB3_SPI1_SCK         (GPIO_MODE_AF0)
#define    PB3_EVENTOUT         (GPIO_MODE_AF1)
#define    PB3_TMR2_CH2         (GPIO_MODE_AF2)
/* PB4 */
#define    PB4_SPI1_MISO        (GPIO_MODE_AF0)
#define    PB4_TMR3_CH1         (GPIO_MODE_AF1)
/* PB5 */
#define    PB5_SPI1_MOSI        (GPIO_MODE_AF0)
#define    PB5_TMR3_CH2         (GPIO_MODE_AF1)
/* PB6 */
#define    PB6_USART1_TX        (GPIO_MODE_AF0)
#define    PB6_TMR3_CH4         (GPIO_MODE_AF2)
/* PB7 */
#define    PB7_USART1_RX        (GPIO_MODE_AF0)
#define    PB7_TMR3_CH3         (GPIO_MODE_AF2)
/* PB8 */
#define    PB8_CANFD_RX         (GPIO_MODE_AF1)
#define    PB8_TMR4_CH3         (GPIO_MODE_AF2)
/* PB9 */
#define    PB9_CANFD_TX         (GPIO_MODE_AF1)
#define    PB9_TMR4_CH4         (GPIO_MODE_AF2)
/* PB10 */
#define    PB10_EVENTOUT        (GPIO_MODE_AF1)
#define    PB10_TMR2_CH3        (GPIO_MODE_AF2)
/* PB11 */
#define    PB11_EVENTOUT        (GPIO_MODE_AF0)
#define    PB11_TMR2_CH4        (GPIO_MODE_AF2)
/* PB12 */
#define    PB12_EVENTOUT        (GPIO_MODE_AF1)
#define    PB12_TMR1_BKIN       (GPIO_MODE_AF2)
/* PB13 */
#define    PB13_TMR2_CH4        (GPIO_MODE_AF1)
#define    PB13_TMR1_CH1N       (GPIO_MODE_AF2)
/* PB14 */
#define    PB14_TMR4_CH1        (GPIO_MODE_AF1)
#define    PB14_TMR1_CH2N       (GPIO_MODE_AF2)
/* PB15 */
#define    PB15_TMR2_CH3        (GPIO_MODE_AF0)
#define    PB15_TMR4_CH2        (GPIO_MODE_AF1)
#define    PB15_TMR1_CH3N       (GPIO_MODE_AF2)
/* PC0 */
#define    PC0_EVENTOUT         (GPIO_MODE_AF0)
#define    PC0_USART2_TX        (GPIO_MODE_AF1)
/* PC1 */
#define    PC1_EVENTOUT         (GPIO_MODE_AF0)
#define    PC1_USART2_RX        (GPIO_MODE_AF1)
/* PC2 */
#define    PC2_EVENTOUT         (GPIO_MODE_AF0)
/* PC3 */
#define    PC3_EVENTOUT         (GPIO_MODE_AF0)
/* PC4 */
#define    PC4_EVENTOUT         (GPIO_MODE_AF0)
/* PC5 */
#define    PC5_TMR1_CH4         (GPIO_MODE_AF2)
/* PC6 */
#define    PC6_TMR3_CH1         (GPIO_MODE_AF0)
/* PC7 */
#define    PC7_TMR3_CH2         (GPIO_MODE_AF0)
/* PC8 */
#define    PC8_TMR3_CH3         (GPIO_MODE_AF0)
/* PC9 */
#define    PC9_TMR3_CH4         (GPIO_MODE_AF0)
/* PC10 */
#define    PC10_TMR1_CH1        (GPIO_MODE_AF2)
/* PC11 */
#define    PC11_TMR1_CH2        (GPIO_MODE_AF2)
/* PC12 */
#define    PC12_TMR1_CH3        (GPIO_MODE_AF2)
/* PC13 */
#define    PC13_TMR1_CH1        (GPIO_MODE_AF2)
/* PC14 */
#define    PC14_TMR1_CH2        (GPIO_MODE_AF2)
/* PC15 */
#define    PC15_TMR1_CH3        (GPIO_MODE_AF2)
/* PD2 */
#define    PD2_TMR1_CH4         (GPIO_MODE_AF2)
/* PF4 */
#define    PF4_EVENTOUT         (GPIO_MODE_AF0)
/* PF5 */
#define    PF5_EVENTOUT         (GPIO_MODE_AF0)
/* PF6 */
#define    PF6_TMR1_CH4         (GPIO_MODE_AF0)
/* PF7 */
#define    PF7_TMR2_CH2         (GPIO_MODE_AF0)

/**@} end of group PORT_Macros */

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif

/**@} end of group PORT_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
