/*!
* @file     Spi_Reg.h
*
* @version  1.0.0
*
* @brief    SPI register header file.This file contains the definitions of SPI Registers and Macros.
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/

#ifndef SPI_REG_H
#define SPI_REG_H

#ifdef __cplusplus
extern "C"{
#endif

#include "Reg_eSys.h"
#include "StdRegMacros.h"
#include "mcal.h"
/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup SPI_Driver
  * @brief SPI driver modules
  @{
*/

/** @defgroup SPI_Macros
  @{
*/
/**************************************************************************
                  VENDOR ID & AUTOSAR VERSION INFO
**************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define SPI_REG_H_VENDOR_ID                       0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */
#define SPI_REG_H_AR_RELEASE_MAJOR_VERSION        0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define SPI_REG_H_AR_RELEASE_MINOR_VERSION        0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define SPI_REG_H_AR_RELEASE_REVISION_VERSION     0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define SPI_REG_H_SW_MAJOR_VERSION                0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define SPI_REG_H_SW_MINOR_VERSION                0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define SPI_REG_H_SW_PATCH_VERSION                0x00U

/**************************************************************************
                    VERSION INFOMATION VERIFICATION
**************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK

    /* Make sure the AUTOSAR major version number is the same between Spi_Reg.h and StdRegMacros.h */
    #if (SPI_REG_H_AR_RELEASE_MAJOR_VERSION != STD_REG_MACROS_H_AR_RELEASE_MAJOR_VERSION) 
         #error "AUTOSAR Major Version Number mismatch between Spi_Reg.h and StdRegMacros.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Spi_Reg.h and StdRegMacros.h */
    #if (SPI_REG_H_AR_RELEASE_MINOR_VERSION != STD_REG_MACROS_H_AR_RELEASE_MINOR_VERSION)
         #error "AUTOSAR Minor Version Number mismatch between Spi_Reg.h and StdRegMacros.h"
    #endif
    
    /* Make sure the AUTOSAR major version number is the same between Spi_Reg.h and Reg_eSys.h */
    #if (SPI_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION) 
         #error "AUTOSAR Major Version Number mismatch between Spi_Reg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Spi_Reg.h and Reg_eSys.h */
    #if (SPI_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
         #error "AUTOSAR Minor Version Number mismatch between Spi_Reg.h and Reg_eSys.h"
    #endif

#endif
 
/**************************************************************************
                    MACRO DEFINITION
**************************************************************************/
/** Macros defined for SPI register operation (start section) */
/** SPI base address */
#define SPI_GET_BASE_ADDR32                          SPI1_BASEADDR

/** Control1 Register (CTRL1) */
#define SPI_CTRL1_ADDRESS_U32                       ((uint32)((uint32)SPI1_BASEADDR + 0x0u))

/** Contro2 Register (CTRL2) */
#define SPI_CTRL2_ADDRESS_U32                       ((uint32)((uint32)SPI1_BASEADDR + 0x0004u))

/** Status Register(STS) */
#define SPI_STS_ADDRESS_U32                         ((uint32)((uint32)SPI1_BASEADDR + 0x0008u))

/** DATA Register (DATA) */
#define SPI_DATA_ADDRESS_U32                        ((uint32)((uint32)SPI1_BASEADDR + 0x000Cu))

/** CRCPOLY Register(CRCPOLY) */
#define SPI_CRCPOLY_ADDRESS_U32                     ((uint32)((uint32)SPI1_BASEADDR + 0x0010u))

/** RXCRC Register(RXCRC) */
#define SPI_RXCRC_ADDRESS_U32                       ((uint32)((uint32)SPI1_BASEADDR + 0x0014u))

/** TXCRC Register(TXCRC) */
#define SPI_TXCRC_ADDRESS_U32                       ((uint32)((uint32)SPI1_BASEADDR + 0x0018u))

/** Macros defined for SPI register read/writes operations */

#define SPI_BITS_MASK                                ((uint32)0xFFFFFFFFu)
#define SPI_BITS_ZERO                                ((uint32)0x00000000u)

/** SPI reserved bit masks */
#define SPI_CTRL1_BITS_MASK                          (SPI_BITS_MASK & ((uint32)0xFFFFu))
#define SPI_CTRL2_BITS_MASK                          (SPI_BITS_MASK & ((uint32)0x7FFFu))
#define SPI_CRCPOLY_BITS_MASK                        (SPI_BITS_MASK & ((uint32)0xFFFFu))

/** Control Register SPI_CTRL1 Sets */
#define SPI_CTRL1_BMEN                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 15)))
#define SPI_CTRL1_BMOEN                              (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 14)))
#define SPI_CTRL1_CRCEN                              (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 13)))
#define SPI_CTRL1_CRCNXT                             (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 12)))
#define SPI_CTRL1_CRCLSEL                            (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 11)))
#define SPI_CTRL1_RXOMEN                             (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 10)))
#define SPI_CTRL1_SSEN                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 9)))
#define SPI_CTRL1_ISSEL                              (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 8)))
#define SPI_CTRL1_LSBSEL                             (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 7)))
#define SPI_CTRL1_SPIEN                              (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 6)))
#define SPI_CTRL1_BRSEL                              (SPI_BITS_MASK & ((uint32)((uint32)0x7U << 3)))
#define SPI_CTRL1_MSMCFG                             (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 2)))
#define SPI_CTRL1_CPOL                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 1)))
#define SPI_CTRL1_CPHA                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 0)))
#define SPI_CTRL1_RESET                              SPI_BITS_ZERO /* Reset register value */

/** Control Register SPI_CTRL2 Sets */
#define SPI_CTRL2_LDTX                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 14)))
#define SPI_CTRL2_LDRX                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 13)))
#define SPI_CTRL2_FRTCFG                             (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 12)))
#define SPI_CTRL2_DSCFG                              (SPI_BITS_MASK & ((uint32)((uint32)0xFU << 8)))
#define SPI_CTRL2_TXBEIEN                            (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 7)))
#define SPI_CTRL2_RXBNEIEN                           (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 6)))
#define SPI_CTRL2_ERRIEN                             (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 5)))
#define SPI_CTRL2_FRFCFG                             (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 4)))
#define SPI_CTRL2_NSSPEN                             (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 3)))
#define SPI_CTRL2_SSOEN                              (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 2)))
#define SPI_CTRL2_TXDEN                              (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 1)))
#define SPI_CTRL2_RXDEN                              (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 0)))
#define SPI_CTRL2_RESET                              (SPI_BITS_ZERO | ((uint32)0x700U)) /* Reset register value */

#define SPI_STS_FTLSEL                               (SPI_BITS_MASK & ((uint32)((uint32)0x3U << 11)))
#define SPI_STS_FRLSEL                               (SPI_BITS_MASK & ((uint32)((uint32)0x3U << 9)))
#define SPI_STS_FREFLG                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 8)))
#define SPI_STS_BSYFLG                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 7)))
#define SPI_STS_OVRFLG                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 6)))
#define SPI_STS_MEFLG                                (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 5)))
#define SPI_STS_CRCEFLG                              (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 4)))
#define SPI_STS_UDRFLG                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 3)))
#define SPI_STS_SCHDIR                               (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 2)))
#define SPI_STS_TXBEFLG                              (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 1)))
#define SPI_STS_RXBNEFLG                             (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 0)))
#define SPI_STS_INT_MASK                             ((uint32)(SPI_STS_TXBEFLG | SPI_STS_RXBNEFLG))

/** Read Transmit FIFO Count Return */
#define SPI_STS_FTLSEL_VAL_U32(value)               (((value) & SPI_STS_FTLSEL) >> 11)
/** Read Receive FIFO Count Return */
#define SPI_STS_FRLSEL_VAL_U32(value)               (((value) & SPI_STS_FRLSEL) >> 9)

/** Data Register SPI_DATA Sets */
#define SPI_DATA                                     (SPI_BITS_MASK & ((uint32)((uint32)0xFFFFU << 0)))

/** Data Register SPI_CRCPOLY Sets */
#define SPI_CRCPOLY                                  (SPI_BITS_MASK & ((uint32)((uint32)0xFFFFU << 0)))

/** Data Register SPI_RXCRC Sets */
#define SPI_RXCRC                                    (SPI_BITS_MASK & ((uint32)((uint32)0xFFFFU << 0)))

/** Data Register SPI_TXCRC Sets */
#define SPI_TXCRC                                    (SPI_BITS_MASK & ((uint32)((uint32)0xFFFFU << 0)))

/** Transmit Command Register(SPI_CTRL1) Sets */
#define SPI_CTRL1_CPOL_LOW                      SPI_BITS_ZERO /* SCK inactive state value:low */
#define SPI_CTRL1_CPOL_HIGH                     (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 1))) /* SCK inactive state value:high */

#define SPI_CTRL1_CPHA_LEADING                  (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 0))) /* Data changed:leading edge;captured:following edge */
#define SPI_CTRL1_CPHA_TRAILING                 SPI_BITS_ZERO /* Data captured:leading edge;changed:following edge */

#define SPI_CTRL1_MSMCFG_DEFAULT                SPI_BITS_ZERO
#define SPI_CTRL1_MSMCFG_SLAVE                  SPI_BITS_ZERO
#define SPI_CTRL1_MSMCFG_MASTER                 (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 2)))

#define SPI_CTRL1_BRSEL_2                         SPI_BITS_ZERO /* Prescaler Value Configure,Divide by 2 */
#define SPI_CTRL1_BRSEL_4                         (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 3))) /* Prescaler Value Configure,Divide by 4 */
#define SPI_CTRL1_BRSEL_8                         (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 4))) /* Prescaler Value Configure,Divide by 8 */
#define SPI_CTRL1_BRSEL_16                        (SPI_BITS_MASK & ((uint32)((uint32)0x3U << 3))) /* Prescaler Value Configure,Divide by 16 */
#define SPI_CTRL1_BRSEL_32                        (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 5))) /* Prescaler Value Configure,Divide by 32 */
#define SPI_CTRL1_BRSEL_64                        (SPI_BITS_MASK & ((uint32)((uint32)0x5U << 3))) /* Prescaler Value Configure,Divide by 64 */
#define SPI_CTRL1_BRSEL_128                       (SPI_BITS_MASK & ((uint32)((uint32)0x6U << 3))) /* Prescaler Value Configure,Divide by 128 */
#define SPI_CTRL1_BRSEL_256                       (SPI_BITS_MASK & ((uint32)((uint32)0x7U << 3))) /* Prescaler Value Configure,Divide by 256 */

#define SPI_CTRL1_SPIEN_DEFAULT                       SPI_BITS_ZERO
#define SPI_CTRL1_SPIEN_DISABLE                       SPI_BITS_ZERO
#define SPI_CTRL1_SPIEN_ENABLE                        (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 6)))

#define SPI_CTRL1_LSBSEL_DEFAULT                      SPI_BITS_ZERO
#define SPI_CTRL1_LSBSEL_MSB                          SPI_BITS_ZERO /* Data MSB transfer first */
#define SPI_CTRL1_LSBSEL_LSB                          (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 7))) /* Data LSB transfer first */

#define SPI_CTRL1_ISSEL_DEFAULT                       SPI_BITS_ZERO
#define SPI_CTRL1_ISSEL_DISABLE                       SPI_BITS_ZERO
#define SPI_CTRL1_ISSEL_ENABLE                        (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 8)))

#define SPI_CTRL1_SSEN_DEFAULT                        SPI_BITS_ZERO
#define SPI_CTRL1_RXOMEN_DEFAULT                      SPI_BITS_ZERO
#define SPI_CTRL1_CRCLSE_DEFAULT                      SPI_BITS_ZERO
#define SPI_CTRL1_CRCNXT_DEFAULT                      SPI_BITS_ZERO
#define SPI_CTRL1_CRCEN_DEFAULT                       SPI_BITS_ZERO
#define SPI_CTRL1_BMOEN_DEFAULT                       SPI_BITS_ZERO
#define SPI_CTRL1_BMEN_DEFAULT                        SPI_BITS_ZERO

#define SPI_CTRL2_LDTX_DEFAULT                        SPI_BITS_ZERO
#define SPI_CTRL2_LDRX_DEFAULT                        SPI_BITS_ZERO

#define SPI_CTRL2_FRTCFG_DEFAULT                      SPI_BITS_ZERO
#define SPI_CTRL2_FRTCFG_16                           SPI_BITS_ZERO
#define SPI_CTRL2_FRTCFG_8                            (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 12)))

#define SPI_CTRL2_DSCFG_DEFAULT                       SPI_BITS_ZERO
#define SPI_CTRL2_DSCFG_0                             SPI_BITS_ZERO
#define SPI_CTRL2_DSCFG_4                             (SPI_BITS_MASK & ((uint32)((uint32)0x3U << 8)))
#define SPI_CTRL2_DSCFG_5                             (SPI_BITS_MASK & ((uint32)((uint32)0x4U << 8)))
#define SPI_CTRL2_DSCFG_6                             (SPI_BITS_MASK & ((uint32)((uint32)0x5U << 8)))
#define SPI_CTRL2_DSCFG_7                             (SPI_BITS_MASK & ((uint32)((uint32)0x6U << 8)))
#define SPI_CTRL2_DSCFG_8                             (SPI_BITS_MASK & ((uint32)((uint32)0x7U << 8)))
#define SPI_CTRL2_DSCFG_9                             (SPI_BITS_MASK & ((uint32)((uint32)0x8U << 8)))
#define SPI_CTRL2_DSCFG_10                            (SPI_BITS_MASK & ((uint32)((uint32)0x9U << 8)))
#define SPI_CTRL2_DSCFG_11                            (SPI_BITS_MASK & ((uint32)((uint32)0xAU << 8)))
#define SPI_CTRL2_DSCFG_12                            (SPI_BITS_MASK & ((uint32)((uint32)0xBU << 8)))
#define SPI_CTRL2_DSCFG_13                            (SPI_BITS_MASK & ((uint32)((uint32)0xCU << 8)))
#define SPI_CTRL2_DSCFG_14                            (SPI_BITS_MASK & ((uint32)((uint32)0xDU << 8)))
#define SPI_CTRL2_DSCFG_15                            (SPI_BITS_MASK & ((uint32)((uint32)0xEU << 8)))
#define SPI_CTRL2_DSCFG_16                            (SPI_BITS_MASK & ((uint32)((uint32)0xFU << 8)))

#define SPI_CTRL2_TXBEIEN_DEFAULT                     SPI_BITS_ZERO
#define SPI_CTRL2_RXBNEIEN_DEFAULT                    SPI_BITS_ZERO
#define SPI_CTRL2_ERRIEN_DEFAULT                      SPI_BITS_ZERO
#define SPI_CTRL2_FRFCFG_DEFAULT                      SPI_BITS_ZERO
#define SPI_CTRL2_NSSPEN_DEFAULT                      SPI_BITS_ZERO

#define SPI_CTRL2_SSOEN_DEFAULT                       SPI_BITS_ZERO
#define SPI_CTRL2_SSOEN_DISABLE                       SPI_BITS_ZERO
#define SPI_CTRL2_SSOEN_ENABLE                        (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 2)))

#define SPI_CTRL2_TXDEN_DEFAULT                       SPI_BITS_ZERO
#define SPI_CTRL2_TXDEN_ENABLE                        (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 1)))

#define SPI_CTRL2_RXDEN_DEFAULT                       SPI_BITS_ZERO
#define SPI_CTRL2_RXDEN_ENABLE                        (SPI_BITS_MASK & ((uint32)((uint32)0x1U << 0)))

#define SPI_CRCPOLY_DEFAULT                           SPI_BITS_ZERO

/**@} end of group SPI_Macros */
#ifdef __cplusplus
}
#endif

#endif /* SPI_REG_H */
/**@} end of group SPI_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */

