/*!
* @file     Usart_Reg.h
*
* @version  1.0.0
*
* @brief    Usart reg header file
*
* @attention
*
* Project Name      : AUTOSAR MCAL
*
* Platform          : Arm
*
* Autosar Standard  : Classic Platform 4.4.0
*
* Compiled Version  : G32A10xx_MCAL_1_0_0_01-Otc-25
*
* Copyright (C) 2026 Geehy Semiconductor
*
* You may not use this file except in compliance with the
* GEEHY COPYRIGHT NOTICE (Geehy Semiconductor Software License Agreement).
*
* The program is only for reference, which is distributed in the hope
* that it will be usefull and instructional for customers to develop
* their software. Unless required by applicable law or agreed to in
* writing, the program is distributed on an "AS IS" BASIS, WITHOUT
* ANY WARRANTY OR CONDITIONS OF ANY KIND, either express or implied.
* See the Geehy Semiconductor Software License Agreement for the governing permissions
* and limitations under the License.
*/


#ifndef USART_REG_H
#define USART_REG_H

#ifdef __cplusplus
extern "C"{
#endif  /* ifdef __cplusplus */

#include "Reg_eSys.h"

/** @addtogroup G32A10xx_StdPeriphDriver
  @{
*/

/** @defgroup USART_Driver
  @{
*/

/** @defgroup USART_Macros
  @{
*/
/***********************************************************************************************************
                                    VENDOR ID & AUTOSAR VERSION INFO
************************************************************************************************************/
/** Vendor ID (vendorId) of the dedicated implementation of this module according to the AUTOSAR vendor list. */
#define USART_REG_H_VENDOR_ID                               0x00C1U
/** Major version number of AUTOSAR release on which the appropriate implementation is based on. */  
#define USART_REG_H_AR_RELEASE_MAJOR_VERSION                0x04U
/** Minor version number of AUTOSAR release on which the appropriate implementation is based on. */
#define USART_REG_H_AR_RELEASE_MINOR_VERSION                0x04U
/** Revision version number of AUTOSAR release on which the appropriate implementation is based on. */
#define USART_REG_H_AR_RELEASE_REVISION_VERSION             0x00U
/** Major version number of the vendor specific implementation of the module. The numbering is vendor specific. */  
#define USART_REG_H_SW_MAJOR_VERSION                        0x01U
/** Minor version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define USART_REG_H_SW_MINOR_VERSION                        0x00U
/** Patch level version number of the vendor specific implementation of the module. The numbering is vendor specific. */
#define USART_REG_H_SW_PATCH_VERSION                        0x00U

/**@} end of group USART_Macros */
/***********************************************************************************************************
                                    VERSION INFOMATION VERIFICATION
************************************************************************************************************/
#ifdef ENABLE_INTERMODULE_MCAL_CHECK
    /* Make sure the AUTOSAR major version number is the same between Usart_Reg.h and Reg_eSys.h */
    #if (USART_REG_H_AR_RELEASE_MAJOR_VERSION != REG_ESYS_H_AR_RELEASE_MAJOR_VERSION)
        #error "AUTOSAR Major Version Number mismatch between Usart_Reg.h and Reg_eSys.h"
    #endif
    /* Make sure the AUTOSAR minor version number is the same between Usart_Reg.h and Reg_eSys.h */
    #if (USART_REG_H_AR_RELEASE_MINOR_VERSION != REG_ESYS_H_AR_RELEASE_MINOR_VERSION)
        #error "AUTOSAR Minor Version Number mismatch between Usart_Reg.h and Reg_eSys.h"
    #endif
#endif

/***********************************************************************************************************
                                        GLOBAL VARIABLE
************************************************************************************************************/
/** @defgroup USART_Variable
  @{
*/

/** The declaration of the UART base address array  */
extern const uint32 USART_BASEADDR_ARR[2];

/**@} end of group USART_Variable */
/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_CTRL1 (Base + 0x00)
************************************************************************************************************/
/** @defgroup USART_Macros
  @{
*/

/** USART_CTRL1 register address */
#define USART_CTRL1_REG_ADDR(ModId)         ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0U))

#define USART_CTRL1_UEN_MASK                ((uint32)0x00000001U)
#define USART_CTRL1_UEN_SHIFT               ((uint8)0U)

#define USART_CTRL1_USWMEN_MASK             ((uint32)0x00000002U)
#define USART_CTRL1_USWMEN_SHIFT            ((uint8)1U)

#define USART_CTRL1_RXEN_MASK               ((uint32)0x00000004U)
#define USART_CTRL1_RXEN_SHIFT              ((uint8)2U)

#define USART_CTRL1_TXEN_MASK               ((uint32)0x00000008U)
#define USART_CTRL1_TXEN_SHIFT              ((uint8)3U)

#define USART_CTRL1_IDLEIEN_MASK            ((uint32)0x00000010U)
#define USART_CTRL1_IDLEIEN_SHIFT           ((uint8)4U)

#define USART_CTRL1_RXBNEIEN_MASK           ((uint32)0x00000020U)
#define USART_CTRL1_RXBNEIEN_SHIFT          ((uint8)5U)

#define USART_CTRL1_TXCIEN_MASK             ((uint32)0x00000040U)
#define USART_CTRL1_TXCIEN_SHIFT            ((uint8)6U)

#define USART_CTRL1_TXBEIEN_MASK            ((uint32)0x00000080U)
#define USART_CTRL1_TXBEIEN_SHIFT           ((uint8)7U)

#define USART_CTRL1_PEIEN_MASK              ((uint32)0x00000100U)
#define USART_CTRL1_PEIEN_SHIFT             ((uint8)8U)

#define USART_CTRL1_PCFG_MASK               ((uint32)0x00000200U)
#define USART_CTRL1_PCFG_SHIFT              ((uint8)9U)

#define USART_CTRL1_PCEN_MASK               ((uint32)0x00000400U)
#define USART_CTRL1_PCEN_SHIFT              ((uint8)10U)

#define USART_CTRL1_WUPMCFG_MASK            ((uint32)0x00000800U)
#define USART_CTRL1_WUPMCFG_SHIFT           ((uint8)11U)

#define USART_CTRL1_DBLCFG0_MASK            ((uint32)0x00001000U)
#define USART_CTRL1_DBLCFG0_SHIFT           ((uint8)12U)

#define USART_CTRL1_RXMUTEEN_MASK           ((uint32)0x00002000U)
#define USART_CTRL1_RXMUTEEN_SHIFT          ((uint8)13U)

#define USART_CTRL1_CMIEN_MASK              ((uint32)0x00004000U)
#define USART_CTRL1_CMIEN_SHIFT             ((uint8)14U)

#define USART_CTRL1_OSMCFG_MASK             ((uint32)0x00008000U)
#define USART_CTRL1_OSMCFG_SHIFT            ((uint8)15U)

#define USART_CTRL1_DDLTEN_MASK             ((uint32)0x001F0000U)
#define USART_CTRL1_DDLTEN_SHIFT            ((uint8)16U)

#define USART_CTRL1_DLTEN_MASK              ((uint32)0x03E00000U)
#define USART_CTRL1_DLTEN_SHIFT             ((uint8)21U)

#define USART_CTRL1_RXTOIEN_MASK            ((uint32)0x04000000U)
#define USART_CTRL1_RXTOIEN_SHIFT           ((uint8)26U)

#define USART_CTRL1_IE_FLAGS_MASK           ((uint32)0x040041f0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_CTRL2 (Base + 0x04)
************************************************************************************************************/
/** USART_CTRL2 register address */
#define USART_CTRL2_REG_ADDR(ModId)         ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0x04U))

#define USART_CTRL2_ADDRLEN_MASK            ((uint32)0x00000010U)
#define USART_CTRL2_ADDRLEN_SHIFT           ((uint8)4U)

#define USART_CTRL2_LBDLCFG_MASK            ((uint32)0x00000020U)
#define USART_CTRL2_LBDLCFG_SHIFT           ((uint8)5U)

#define USART_CTRL2_LBDIEN_MASK             ((uint32)0x00000040U)
#define USART_CTRL2_LBDIEN_SHIFT            ((uint8)6U)

#define USART_CTRL2_LBCPOEN_MASK            ((uint32)0x00000100U)
#define USART_CTRL2_LBCPOEN_SHIFT           ((uint8)8U)

#define USART_CTRL2_CPHA_MASK               ((uint32)0x00000200U)
#define USART_CTRL2_CPHA_SHIFT              ((uint8)9U)

#define USART_CTRL2_CPOL_MASK               ((uint32)0x00000400U)
#define USART_CTRL2_CPOL_SHIFT              ((uint8)10U)

#define USART_CTRL2_CLKEN_MASK              ((uint32)0x00000800U)
#define USART_CTRL2_CLKEN_SHIFT             ((uint8)11U)

#define USART_CTRL2_STOPCFG_MASK            ((uint32)0x00003000U)
#define USART_CTRL2_STOPCFG_SHIFT           ((uint8)12U)

#define USART_CTRL2_LINMEN_MASK             ((uint32)0x00004000U)
#define USART_CTRL2_LINMEN_SHIFT            ((uint8)14U)

#define USART_CTRL2_SWAPEN_MASK             ((uint32)0x00008000U)
#define USART_CTRL2_SWAPEN_SHIFT            ((uint8)15U)

#define USART_CTRL2_RXINVEN_MASK            ((uint32)0x00010000U)
#define USART_CTRL2_RXINVEN_SHIFT           ((uint8)16U)

#define USART_CTRL2_TXINVEN_MASK            ((uint32)0x00020000U)
#define USART_CTRL2_TXINVEN_SHIFT           ((uint8)17U)

#define USART_CTRL2_BINVEN_MASK             ((uint32)0x00040000U)
#define USART_CTRL2_BINVEN_SHIFT            ((uint8)18U)

#define USART_CTRL2_MSBFEN_MASK             ((uint32)0x00080000U)
#define USART_CTRL2_MSBFEN_SHIFT            ((uint8)19U)

#define USART_CTRL2_ABRDEN_MASK             ((uint32)0x00100000U)
#define USART_CTRL2_ABRDEN_SHIFT            ((uint8)20U)

#define USART_CTRL2_ABRDCFG_MASK            ((uint32)0x00600000U)
#define USART_CTRL2_ABRDCFG_SHIFT           ((uint8)21U)

#define USART_CTRL2_RXTODEN_MASK            ((uint32)0x00800000U)
#define USART_CTRL2_RXTODEN_SHIFT           ((uint8)23U)

#define USART_CTRL2_ADDRL_MASK              ((uint32)0x0F000000U)
#define USART_CTRL2_ADDRL_SHIFT             ((uint8)24U)

#define USART_CTRL2_ADDRH_MASK              ((uint32)0xF0000000U)
#define USART_CTRL2_ADDRH_SHIFT             ((uint8)28U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_CTRL3 (Base + 0x08)
************************************************************************************************************/
/** USART_CTRL3 register address */
#define USART_CTRL3_REG_ADDR(ModId)         ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0x08U))

#define USART_CTRL3_ERRIEN_MASK             ((uint32)0x00000001U)
#define USART_CTRL3_ERRIEN_SHIFT            ((uint8)0U)

#define USART_CTRL3_HDEN_MASK               ((uint32)0x00000008U)
#define USART_CTRL3_HDEN_SHIFT              ((uint8)3U)

#define USART_CTRL3_DMARXEN_MASK            ((uint32)0x00000040U)
#define USART_CTRL3_DMARXEN_SHIFT           ((uint8)6U)

#define USART_CTRL3_DMATXEN_MASK            ((uint32)0x00000080U)
#define USART_CTRL3_DMATXEN_SHIFT           ((uint8)7U)

#define USART_CTRL3_RTSEN_MASK              ((uint32)0x00000100U)
#define USART_CTRL3_RTSEN_SHIFT             ((uint8)8U)

#define USART_CTRL3_CTSEN_MASK              ((uint32)0x00000200U)
#define USART_CTRL3_CTSEN_SHIFT             ((uint8)9U)

#define USART_CTRL3_CTSIEN_MASK             ((uint32)0x00000400U)
#define USART_CTRL3_CTSIEN_SHIFT            ((uint8)10U)

#define USART_CTRL3_SAMCFG_MASK             ((uint32)0x00000800U)
#define USART_CTRL3_SAMCFG_SHIFT            ((uint8)11U)

#define USART_CTRL3_OVRDEDIS_MASK           ((uint32)0x00001000U)
#define USART_CTRL3_OVRDEDIS_SHIFT          ((uint8)12U)

#define USART_CTRL3_DDISRXEEN_MASK          ((uint32)0x00002000U)
#define USART_CTRL3_DDISRXEEN_SHIFT         ((uint8)13U)

#define USART_CTRL3_DEN_MASK                ((uint32)0x00004000U)
#define USART_CTRL3_DEN_SHIFT               ((uint8)14U)

#define USART_CTRL3_DPCFG_MASK              ((uint32)0x00008000U)
#define USART_CTRL3_DPCFG_SHIFT             ((uint8)15U)

#define USART_CTRL3_WSIFLGSEL_MASK          ((uint32)0x00300000U)
#define USART_CTRL3_WSIFLGSEL_SHIFT         ((uint8)20U)

#define USART_CTRL3_WSMIEN_MASK             ((uint32)0x00400000U)
#define USART_CTRL3_WSMIEN_SHIFT            ((uint8)22U)

#define USART_CTRL3_IE_FLAGS_MASK           ((uint32)0x00400401U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_BR (Base + 0x0C)
************************************************************************************************************/
/** USART_BR register address */
#define USART_BR_REG_ADDR(ModId)            ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0x0CU))

#define USART_BR_FBR_MASK                   ((uint32)0x0000000FU)
#define USART_BR_FBR_SHIFT                  ((uint8)0U)

#define USART_BR_IBR_MASK                   ((uint32)0x0000FFF0U)
#define USART_BR_IBR_SHIFT                  ((uint8)4U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_RXTO (Base + 0x14)
************************************************************************************************************/
/** USART_RXTO register address */
#define USART_RXTO_REG_ADDR(ModId)          ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0x14U))

#define USART_RXTO_RXTO_MASK                ((uint32)0x00FFFFFFU)
#define USART_RXTO_RXTO_SHIFT               ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_REQUEST (Base + 0x18)
************************************************************************************************************/
/** USART_REQUEST register address */
#define USART_REQUEST_REG_ADDR(ModId)       ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0x18U))

#define USART_REQUEST_ABRDQ_MASK            ((uint32)0x00000001U)
#define USART_REQUEST_ABRDQ_SHIFT           ((uint8)0U)

#define USART_REQUEST_TXBFQ_MASK            ((uint32)0x00000002U)
#define USART_REQUEST_TXBFQ_SHIFT           ((uint8)1U)

#define USART_REQUEST_MUTEQ_MASK            ((uint32)0x00000004U)
#define USART_REQUEST_MUTEQ_SHIFT           ((uint8)2U)

#define USART_REQUEST_RXDFQ_MASK            ((uint32)0x00000008U)
#define USART_REQUEST_RXDFQ_SHIFT           ((uint8)3U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_STS (Base + 0x1C)
************************************************************************************************************/
/** USART_STS register address */
#define USART_STS_REG_ADDR(ModId)           ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0x1CU))

#define USART_STS_PEFLG_MASK                ((uint32)0x00000001U)
#define USART_STS_PEFLG_SHIFT               ((uint8)0U)

#define USART_STS_FEFLG_MASK                ((uint32)0x00000002U)
#define USART_STS_FEFLG_SHIFT               ((uint8)1U)

#define USART_STS_NEFLG_MASK                ((uint32)0x00000004U)
#define USART_STS_NEFLG_SHIFT               ((uint8)2U)

#define USART_STS_OVREFLG_MASK              ((uint32)0x00000008U)
#define USART_STS_OVREFLG_SHIFT             ((uint8)3U)

#define USART_STS_IDLEFLG_MASK              ((uint32)0x00000010U)
#define USART_STS_IDLEFLG_SHIFT             ((uint8)4U)

#define USART_STS_RXBNEFLG_MASK             ((uint32)0x00000020U)
#define USART_STS_RXBNEFLG_SHIFT            ((uint8)5U)

#define USART_STS_TXCFLG_MASK               ((uint32)0x00000040U)
#define USART_STS_TXCFLG_SHIFT              ((uint8)6U)

#define USART_STS_TXBEFLG_MASK              ((uint32)0x00000080U)
#define USART_STS_TXBEFLG_SHIFT             ((uint8)7U)

#define USART_STS_LBDFLG_MASK               ((uint32)0x00000100U)
#define USART_STS_LBDFLG_SHIFT              ((uint8)8U)

#define USART_STS_CTSFLG_MASK               ((uint32)0x00000200U)
#define USART_STS_CTSFLG_SHIFT              ((uint8)9U)

#define USART_STS_CTSCFG_MASK               ((uint32)0x00000400U)
#define USART_STS_CTSCFG_SHIFT              ((uint8)10U)

#define USART_STS_RXTOFLG_MASK              ((uint32)0x00000800U)
#define USART_STS_RXTOFLG_SHIFT             ((uint8)11U)

#define USART_STS_ABRDEFLG_MASK             ((uint32)0x00004000U)
#define USART_STS_ABRDEFLG_SHIFT            ((uint8)14U)

#define USART_STS_ABRDFLG_MASK              ((uint32)0x00008000U)
#define USART_STS_ABRDFLG_SHIFT             ((uint8)15U)

#define USART_STS_BSYFLG_MASK               ((uint32)0x00010000U)
#define USART_STS_BSYFLG_SHIFT              ((uint8)16U)

#define USART_STS_CMFLG_MASK                ((uint32)0x00020000U)
#define USART_STS_CMFLG_SHIFT               ((uint8)17U)

#define USART_STS_TXBFFLG_MASK              ((uint32)0x00040000U)
#define USART_STS_TXBFFLG_SHIFT             ((uint8)18U)

#define USART_STS_RXWFMUTE_MASK             ((uint32)0x00080000U)
#define USART_STS_RXWFMUTE_SHIFT            ((uint8)19U)

#define USART_STS_WSMFLG_MASK               ((uint32)0x00100000U)
#define USART_STS_WSMFLG_SHIFT              ((uint8)20U)

#define USART_STS_TXENACKFLG_MASK           ((uint32)0x00200000U)
#define USART_STS_TXENACKFLG_SHIFT          ((uint8)21U)

#define USART_STS_RXENACKFLG_MASK           ((uint32)0x00400000U)
#define USART_STS_RXENACKFLG_SHIFT          ((uint8)22U)

#define USART_STS_INT_FLAGS_MASK            ((uint32)0x000401e0U)
#define USART_STS_ERR_FLAGS_MASK            ((uint32)0x000fU)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_INTFCLR (Base + 0x20)
************************************************************************************************************/
/** USART_INTFCLR register address */
#define USART_INTFCLR_REG_ADDR(ModId)       ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0x20U))

#define USART_INTFCLR_PECLR_MASK            ((uint32)0x00000001U)
#define USART_INTFCLR_PECLR_SHIFT           ((uint8)0U)

#define USART_INTFCLR_FECLR_MASK            ((uint32)0x00000002U)
#define USART_INTFCLR_FECLR_SHIFT           ((uint8)1U)

#define USART_INTFCLR_NECLR_MASK            ((uint32)0x00000004U)
#define USART_INTFCLR_NECLR_SHIFT           ((uint8)2U)

#define USART_INTFCLR_OVRECLR_MASK          ((uint32)0x00000008U)
#define USART_INTFCLR_OVRECLR_SHIFT         ((uint8)3U)

#define USART_INTFCLR_IDLECLR_MASK          ((uint32)0x00000010U)
#define USART_INTFCLR_IDLECLR_SHIFT         ((uint8)4U)

#define USART_INTFCLR_TXCCLR_MASK           ((uint32)0x00000040U)
#define USART_INTFCLR_TXCCLR_SHIFT          ((uint8)6U)

#define USART_INTFCLR_LBDCLR_MASK           ((uint32)0x00000100U)
#define USART_INTFCLR_LBDCLR_SHIFT          ((uint8)8U)

#define USART_INTFCLR_CTSCLR_MASK           ((uint32)0x00000200U)
#define USART_INTFCLR_CTSCLR_SHIFT          ((uint8)9U)

#define USART_INTFCLR_RXTOCLR_MASK          ((uint32)0x00000800U)
#define USART_INTFCLR_RXTOCLR_SHIFT         ((uint8)11U)

#define USART_INTFCLR_CMCLR_MASK            ((uint32)0x00020000U)
#define USART_INTFCLR_CMCLR_SHIFT           ((uint8)17U)

#define USART_INTFCLR_WSMCLR_MASK           ((uint32)0x00100000U)
#define USART_INTFCLR_WSMCLR_SHIFT          ((uint8)20U)

#define USART_INTFCLR_MASK                  ((uint32)0x00120b5FU)
#define USART_INTFCLR_ERR_FLAGS_MASK        ((uint32)0xFU)
/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_RXDATA (Base + 0x24)
************************************************************************************************************/
/** USART_RXDATA register address */
#define USART_RXDATA_REG_ADDR(ModId)        ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0x24U))

#define USART_RXDATA_RXDATA_MASK            ((uint32)0x000001FFU)
#define USART_RXDATA_RXDATA_SHIFT           ((uint8)0U)

/***********************************************************************************************************
        BIT MASK AND OFFSET FOR REGISTER: USART_TXDATA (Base + 0x28)
************************************************************************************************************/
/** USART_TXDATA register address */
#define USART_TXDATA_REG_ADDR(ModId)        ((uint32)(USART_BASEADDR_ARR[ModId] + (uint32)0x28U))

#define USART_TXDATA_TXDATA_MASK            ((uint32)0x000001FFU)
#define USART_TXDATA_TXDATA_SHIFT           ((uint8)0U)

/**@} end of group USART_Macros */

#ifdef __cplusplus
}
#endif  /* __cplusplus */

#endif  /* USART_REG_H */

/**@} end of group USART_Driver */
/**@} end of group G32A10xx_StdPeriphDriver */
